METHOD FOR PRODUCING A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP

Abstract

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

Claims

1. Method for producing a semiconductor chip, in which, during a growth process for growing a first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer, such that a lateral variation of a material composition of the first semiconductor layer is produced.

2. Method according to claim 1, in which the inhomogeneous lateral temperature distribution is selectively created, at least partly, by a locally varying light irradiation.

3. Method according to claim 2, in which the light irradiation comprises an irradiation with a laser.

4. Method according to claim 2, in which the light irradiation is varied locally by a light deflecting means and/or by a plurality of light sources that can be operated independently of one another, to create the inhomogeneous lateral temperature distribution.

5. Method according to claim 1, in which the inhomogeneous lateral temperature distribution is selectively created, at least partly, by a temperature distribution structure, which has at least one temperature distribution structure element, which effects a local increase or reduction of the temperature of the growing first semiconductor layer.

6. Method according to claim 5, in which the first semiconductor layer is grown on a growth substrate, and the temperature distribution structure is arranged on a side of the growth substrate that faces away from the first semiconductor layer.

7. Method according to claim 5, in which the first semiconductor layer is grown on a growth substrate, and the temperature distribution structure is arranged on a side of the growth substrate that faces toward the first semiconductor layer.

8. Method according to claim 5, in which the temperature distribution structure is arranged in direct contact with the growth substrate.

9. Method according to claim 5, in which, as viewed from the growth substrate, the temperature distribution structure is covered by a protective layer, and/or a protective layer is arranged between the temperature distribution structure and the growth substrate.

10. Method according to claim 5, in which the temperature distribution structure is embedded into a protective layer.

11. Method according to claim 5, in which the temperature distribution structure is embedded in a semiconductor layer and/or in a growth substrate.

12. Method according to claim 5, in which the temperature distribution structure remains in the finished semiconductor chip.

13. Method according to claim 5, in which the temperature distribution structure element has a material that absorbs electromagnetic radiation.

14. Method according to claim 5, in which the temperature distribution structure element has an elevation and/or a recess in a growth substrate.

15. Method according to claim 5, in which the temperature distribution structure element has a recess, in a growth substrate, arranged in which there is a thermal barrier material having a lesser thermal conductivity than the growth substrate.

16. Method according to claim 5, in which the temperature distribution structure element has an elevation, in a growth substrate, which effects a locally varying thermal coupling to a carrier, on which the growth substrate is arranged.

17. Method according to claim 1, in which the first semiconductor layer is at least a part of a waveguide layer and/or of an active layer.

18. Method according to claim 1, in which at least one second semiconductor layer is grown over the first semiconductor layer and a ridge waveguide is created in the second semiconductor layer.

19. Method according to claim 1, in which the first semiconductor layer is part of a semiconductor layer sequence having a plurality of semiconductor layers.

20. Semiconductor chip produced by means of a method according to claim 1, having a first semiconductor layer that, along at least one direction of extent, has a lateral variation of a material composition resulting from a laterally varying temperature distribution during a growth process.

Description

IN THE FIGURES

[0048] FIG. 1 is a schematic representation of a method for producing a semiconductor chip according to the exemplary embodiment,

[0049] FIGS. 2A to 2H are schematic representations of semiconductor chips according to a plurality of exemplary embodiments,

[0050] FIGS. 3A to 6F are schematic representations of features of methods for producing semiconductor chips according to further exemplary embodiments.

[0051] In the exemplary embodiments and figures, elements that are the same, of the same type or have the same effect are in each case denoted by the same references. The elements represented and their relative size ratios are not to be regarded as true to scale, but instead the size of individual elements such as, for example, layers, components, devices and regions may be exaggerated to aid illustration and/or to aid comprehension.

[0052] Shown in FIG. 1 is a method for producing a semiconductor chip according to one exemplary embodiment, in which the semiconductor chip is produced with a first semiconductor layer having a lateral variation of the material composition. For this purpose, in a first method step 1000, a surface is provided, on which the first semiconductor layer is grown. The first semiconductor layer may preferably be part of a semiconductor layer sequence, which, in addition to the first semiconductor layer, has a plurality of further semiconductor layers. The surface provided for growing the first semiconductor layer may be formed by a growth substrate, or a semiconductor layer that is grown on the growth substrate and that may also be part of an already grown sub-layer stack of the semiconductor layer sequence.

[0053] In a further method step 2000, the first semiconductor layer sequence is grown on the provided surface. This may also mean that, before growing of the first semiconductor layer, one or more further semiconductor layers of the semiconductor layer sequence may be grown on the surface. During the growth process for growing the first semiconductor layer, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer. The inhomogeneous lateral temperature distribution during the growth process causes a lateral variation of the material composition of the first semiconductor layer. This means, in other words, that the material that is provided and supplied for growing the first semiconductor layer is deposited, in the course of the growth process, on at least two or more surface regions of the provided surface, which have differing temperatures. The composition of the growing material is dependent on the local temperature of the respective surface region, such that the differing temperatures in the at least two or more surface regions result in differing material compositions. Accordingly, the first semiconductor layer has at least two or more regions of differing material compositions, which are arranged laterally next to each other along at least one direction of extent of the first semiconductor layer. The temperature differences between the surface regions of the provided surface many be greater than or equal to 1 K, or greater than or equal to 2 K, or greater than or equal to 5 K, or even greater than or equal to 10 K. Between two adjacent surface regions having differing temperatures, the surface temperature may change abruptly, i.e. insofar as technically possible, substantially in a stepped manner, or continuously, having a desired temperature profile.

[0054] In a further method step 3000, following the growing of the first semiconductor layer having the lateral variation of the material composition, the semiconductor chip is completed. This may mean, for example, that, inter alia, one or more further semiconductor layers of the semiconductor layer sequence and/or one or more passivation layers and/or one or more contact layers are applied. Alternatively or additionally, other process steps such as, for example, etching processes and other structuring processes, as well as singulation steps for singulating a wafer composite into individual semiconductor chips, are performed.

[0055] Further features of the method for producing the semiconductor chip, and further features of the semiconductor chip thus produced, are described in the following figures. The exemplary embodiments described in the following, however, are not to be understood such that they limit the possible method features, and the features of the semiconductor chip produced by the method, only to the features specifically described in the following. Rather, the following exemplary embodiments are to be understood as purely exemplary for possible method features and for features of the semiconductor chips that can be produced by the method.

[0056] Described in conjunction with FIGS. 2A to 2H are exemplary embodiments for semiconductor chips 100, which are produced by a method according to the exemplary embodiment of FIG. 1, i.e. a method in which, during a growth process for growing a first semiconductor layer 1, an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer 1, such that a lateral variation of a material composition of the first semiconductor layer 1 is produced. The semiconductor chips 100 shown thus have a first semiconductor layer 1 that, along at least one direction of extent, has a lateral variation of a material composition resulting from a laterally varying temperature distribution during a growth process.

[0057] In the exemplary embodiments shown, the first semiconductor layer 1 is, purely exemplarily, part of a semiconductor layer sequence that, in addition to the first semiconductor layer 1, has a second semiconductor layer 2 and a third layer 3, between which the first semiconductor layer 1 is arranged. Each of the layers 1, 2, 3 of the semiconductor layer sequence may have one or more layers, or be composed thereof. The layers of the semiconductor layer sequence are arranged on one another along a direction of growth. The direction of growth may also be referred to as the vertical direction. Perpendicularly to the direction of growth, the layers of the semiconductor layer sequence have an extent along directions of extent in the lateral direction, the lateral extent preferably being greater than the thickness of the layers in the vertical direction. The semiconductor layer sequence can be grown, in particular, in the wafer composite, which can subsequently be singulated into a multiplicity of semiconductor chips 100.

[0058] For example, the third layer 3 may have a substrate, which may be electrically conductive or electrically insulating, and on which the further layers of the semiconductor layer sequence are applied. The substrate may be a growth substrate, described in the general part above, on which the semiconductor layers of the semiconductor layer sequence are grown by means of an epitaxial growth method such as, for example, MOVPE or MBE. As an alternative to this, the substrate may be a so-called carrier substrate, onto which the semiconductor layers of the semiconductor layer sequence are transferred after having been grown on a growth substrate. Following the growing process, the growth substrate may be thinned or removed completely, such that can also be possible for the layer 3 in the finished semiconductor chip 100 to have no substrate.

[0059] In the exemplary embodiments shown, the semiconductor chips 100 are embodied, purely exemplarily, as edge-emitting laser diode chips, having an active layer for generating light, in particular laser light. The first semiconductor layer 1 in this case may be formed, in particular, by at least a part of a waveguide layer and/or of the active layer. In other words, the first semiconductor layer 1 may be a part of a waveguide layer, and/or a part of an active layer, and/or be or have a waveguide layer, and/or be or have an active layer. Furthermore, the first semiconductor layer 1 may also be formed by a plurality of layers that together form a part of a waveguide layer, and/or at least a part of an active layer, and/or a waveguide layer, and/or an active layer.

[0060] In addition to having the first semiconductor layer 1, the semiconductor layer sequence of the semiconductor chip 100 may have further functional semiconductor chips such as, for example, one or more layers selected from waveguide layers, cladding layers, buffer layers and semiconductor contact layers, which may be part of the second semiconductor layer 2 and third layer 3, or which, singly or in combination, may form the second semiconductor layer 2 and the third layer 3 of the semiconductor layer sequence. Furthermore, the first semiconductor layer 1 may also have such a layer.

[0061] Applied on the semiconductor layer sequence there is contact layer 4, which has a bondable and/or solderable metal, for electrically contacting the semiconductor chip 100. The contact layer 4 may also have a corresponding layer sequence of a plurality of metal layers. The term “metal”, apart from denoting a pure metal, may also denote mixtures, alloys and compounds having or composed of a plurality of metals that have properties suitable for electrical contacting and for electrical connection. Suitable metals for the contact layer 4 may be, singly or in combination, one or more selected from gold, aluminum, silver, titanium, platinum, nickel, palladium, rhodium and tungsten.

[0062] The semiconductor chip 100 have at least one further contact layer, which for reasons of clarity is not shown in the FIGS. 2A to 2H and which, together with the contact layer 4, enable electrical connection of the semiconductor chip 100 to be effected. For example, the third layer 3 may be electrically conductive, and the further contact layer is applied on a side of the third layer 3 that faces away from the first semiconductor layer 1. Alternatively, the further contact layer may be arranged on a correspondingly exposed part of the surface of the semiconductor chip 100, next to the contact layer 4 shown.

[0063] In at least some exemplary embodiments, the semiconductor chips 100 have, in regions, i.e. in sub-regions between the contact layer 4 and the semiconductor layer sequence, a passivation layer 5, which electrically insulates a part of the surface of the semiconductor layer sequence against the contact layer 4. The passivation layer 5 may be, or be composed of, for example, an electrically insulating oxide, nitride or oxynitride, or a combination of such materials. For example, the passivation layer may have one or more of the following materials: aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, titanium oxide. The passivation layer 5 makes it possible to provide a contact layer 4 having a large contact surface, which is large enough for external electrical contacting of the semiconductor chip 100, for example by means of a soldered connection or a bond wire, while the semiconductor layer sequence is electrically connected, in a smaller region, by the electrical contact layer 4. The contact region between the contact layer 4 and the semiconductor layer sequence may define, in particular, the region of the active layer in which it is sought to generate light, and may be embodied accordingly, for example in the form of a strip. The strip-type contact region may preferably extend from a front side face of the semiconductor layer sequence, which forms a coupling-out facet for light emission, to an oppositely located, rear side face of the semiconductor layer sequence, which forms a reflective rear-side facet. Appropriate layers such as, for example, partially or fully reflective layers, and layer combinations, according to the required functionalities, may be applied on the facets.

[0064] Purely exemplarily, the first semiconductor layer 1, and preferably the semiconductor layer sequence of the semiconductor chip 100, are based on the III-V compound semiconductor material system InAlGaN, described above in the general part. Thus, in the exemplary embodiments shown, the material composition of the first semiconductor layer 1 in this case may vary in the lateral direction with respect to at least one of the crystal constituents of InAlGaN. Particularly preferably, the material composition varies with respect to the indium content, which is particularly dependent on the growth temperature. Thus, in the case of usual growth temperatures, the incorporated indium content may become less as the growth temperature increases, such that, in regions of the growing first semiconductor layer 1 in which there prevails a lesser growth temperature, in comparison with other regions, it is possible to effect a greater incorporation of indium and, consequently, a resultant greater indium content.

[0065] In dependence on the lateral variation of the material composition along at least one direction of extent, properties of the first semiconductor layer 1 may vary along this direction of extent. In the material system InAlGaN, for example, a higher indium content may result in a higher refractive index, a reduction of the band gap and an increase of the optical absorption. Correspondingly, a higher indium content may result in a reduction of the refractive index, an increase of the band gap and a reduction of the optical absorption.

[0066] Particularly preferably, in the exemplary embodiments shown, as represented in the figures, the layer thickness of the first semiconductor layer 1 may be constant. In particular, irrespective of the material composition of differing regions, as described in the following, the thickness of the first semiconductor layer 1 may vary by not more than 10% or by not more than 5% or, particularly preferably, by not more than 1%.

[0067] The semiconductor chip 100 shown in FIG. 2A is embodied as a so-called single-emitter oxide strip laser, and has a semiconductor layer 1, having regions 11, 12, arranged laterally next to each other, that have differing material compositions. The region 11 is embodied in the form of a strip, corresponding to the contact region, arranged above it, between the semiconductor layer sequence and the contact layer 4, and in the lateral direction, transversely in relation to the direction of extent of the strip, adjoins the regions 12. As viewed toward the coupling-out facet or the rear-side face of the semiconductor chip 100, the regions 12 are thus arranged on the left and right, next to the region 11. The region 11, which, as viewed toward the coupling-out facet, may have a width in the range of from some micrometers up to some 10 μm, and which corresponds substantially to the region provided for light generation, has a greater indium content than the laterally adjacent regions 12, such that the regions 12 have a lower refractive index and a greater band gap than the region 11. This difference in the refractive index and in the band gap make it possible, when the semiconductor chip 100 is in operation, to achieve an index guiding of the light generated in the active layer that is already “incorporated” in the semiconductor chip 100 following the epitaxial growth. It is thereby possible for an index guiding to be achieved without a ridge waveguide structure, usual in the prior art, such that the etching process associated therewith is not necessary.

[0068] In the case of usual ridge waveguide structures, the etching depth must be kept precisely to a few nanometers, since an excessively flat etching can cause current spread, and consequently weak guidance, which may be reflected in impaired performance, lesser characteristic linearity and reduced yield, while an excessively deep etching may result in stability problems and non-linearities in the dependence of operating current on light output, so-called “kinks”. Accordingly, the etching process for producing conventional ridge waveguide structures represents an elaborate production process. Furthermore, the forming of a metallic contact layer over the conventional ridge waveguide structure can be critical, and increase the risk of so-called erosion. Owing to the surface structure formed by a conventional ridge waveguide structure, there may furthermore be heating problems in the case of the laser diode chip being mounted with the ridge side downward.

[0069] As a result of the index guiding being incorporated into the first semiconductor layer 1, in the form of a planar structure, during the growth process, an improved yield, a better laser performance, an improved characteristic linearity and a greater component stability can be obtained for the thus produced semiconductor chip 100, with regard to the described problems of ridge etching. In addition, the production process can be simpler than in the case of a conventional laser diode having a ridge waveguide structure. Furthermore, the application of the contact layer 4, and consequently the forming of a metallic layer over the semiconductor layer sequence is simpler and less susceptible to error, which may be reflected in a greater stability. In addition, the planar structure, provided for index guiding, produced in the first semiconductor layer 1, which results in a correspondingly planar structure for the contact layer 4 also, can result in improved heating in the case of the semiconductor chip 100 being mounted with the contact layer 4 downward.

[0070] The semiconductor chip 100 shown in FIG. 2B is embodied as a so-called single-emitter wide-strip laser and, in comparison with the exemplary embodiment of FIG. 2A, has a wider region 11 having a higher indium content, as compared with the laterally adjoining regions 12 on the left and right. The wider region 11 corresponds substantially to the, in comparison with the exemplary embodiment of FIG. 2A, now likewise wider, active region, which is provided for light generation. Owing to the greater width of the region provided for light generation, a contact layer 4 that is also sufficiently wide for external contacting can be applied on the semiconductor layer sequence without a passivation layer 5 arranged in between. The semiconductor chip 100 shown in FIG. 2B is accordingly characterized by very simple processing and, at the same time, an improved laser performance, in comparison with the prior art, due to the integrated waveguiding already described in conjunction with FIG. 2A.

[0071] Shown in FIGS. 2C to 2E are semiconductor chips 100 that, in comparison with the previous exemplary embodiments, and in particular in comparison with the exemplary embodiment of FIG. 2A, have, over the first semiconductor layer 1, a second semiconductor layer 2, which, over the region 11 having the increased indium content, additionally have a ridge waveguide structure 21. This structure, in combination with the waveguiding already incorporated in the first semiconductor layer 1 by the described growth process, makes it possible to achieve an improved yield, a higher laser performance and improved far-field properties. In comparison with conventional laser diodes, which have only a ridge waveguide structure, in the case of the semiconductor chips 100 of the exemplary embodiments of FIGS. 2C to 2E, moreover, a lesser etching depth is required in the production of the ridge, which can result in a better ageing stability and lesser susceptibility to faults in the production process.

[0072] The width of the region 11 can be varied, in comparison with the width of the ridge waveguide structure 21, by differing extents of lateral variations of the growth temperature during the growth process for producing the first semiconductor layer 1, whereby differing component properties can be produced by one same production process. As shown in FIG. 2C, the region 11 and the ridge waveguide structure 21 may be of the same, or at least substantially the same, width. As shown in FIGS. 2D and 2E, the width of the region 11 may also be greater or less than the width of the ridge waveguide structure 21.

[0073] As described in connection with the exemplary embodiments of FIGS. 2A to 2E, it is possible either to dispense with a ridge waveguide structure, or the depth of the ridge etching can be reduced significantly, since both the current limiting and the index guiding can be incorporated in the semiconductor chip 100. Furthermore, it may be the case that, if necessary, the contact layer 4 must at most be partially removed, as shown in FIG. 2B.

[0074] Shown in conjunction with FIGS. 2F to 2H are further exemplary embodiments of semiconductor chips 100 that, in comparison with the previous exemplary embodiments, form multi-emitting laser diode chips in the form of laser bars and laser arrays.

[0075] FIG. 2F shows a semiconductor chip 100 that is embodied as a multi-emitting laser bar, having a first semiconductor layer 1, which has a plurality of strip-type regions 11 of higher indium content, which are arranged laterally next to each other, which correspond to a plurality of regions for light generation, and which are separated from each other by regions 12 having a lower indium content. In the case of wide-strip lasers, in particular, an improved mode control and an improved far-field behavior can thereby be achieved. The contacting of the plurality of regions 11 is effected via a common contact layer 4.

[0076] FIG. 2G shows a semiconductor chip 100 in which the contact layer 4, in a plurality of mutually adjacent strip-type contact regions, contacts the semiconductor layer sequence. The contact regions correspond to a plurality of active regions in the active layer that can be operated jointly. The first semiconductor layer 1 has regions 11, 12 of differing material composition, in particular differing indium content, which merge continuously into each other and overlay the “conventional” active zone. It is thereby made possible to modify the wave guiding along the array strip such that temperature effects can be balanced out in operation of the array. Thus, for example, in the case of a usual multi-emitting laser array, the active regions in the middle of the array become warmer, which results in a higher refractive index and consequently altered wave guiding. This can be counteracted by the laterally varying material composition of the first semiconductor layer 1, in that, for example in the peripheral region, i.e. in the regions 12, a higher refractive index is incorporated by a laterally varying growth temperature during the growth of the first semiconductor layer 1, by an increased incorporation of indium in comparison with the region 11. It is thereby made possible, when the semiconductor chip 100 is in operation, for all active regions to have comparable wave guiding and/or wavelength characteristics.

[0077] FIG. 2H shows a semiconductor chip 100 that allows separate operation of active regions by a plurality of mutually separate contact layers 4. The active regions in this case correspond to regions 11 that, in comparison with adjacent regions 12, 13, 14, have a higher indium content. Furthermore, the indium content decreases continuously from the regions 14, via the regions 13, to the region 12, such that the advantages described in connection with the preceding exemplary embodiments can be achieved, i.e. an internal index guiding and a balancing-out of differing wave guiding characteristics that can be caused by the prevailing temperature profile during operation of the semiconductor chip 100.

[0078] Possibilities for producing inhomogeneous lateral temperature distributions for growing the first semiconductor layer are described in conjunction with the following figures. The inhomogeneous lateral temperature distribution is selectively produced, during the growing of the first semiconductor layer, by local thermal influencing of predefined and specifically selected regions. In particular, the inhomogeneous lateral temperature distribution may be produced, at least partly, by a temperature distribution structure and/or by a locally varying light irradiation, as described in the following. If a temperature distribution structure is used, this can remain according to the arrangement in the semiconductor chip. Accordingly, the previously described semiconductor chips may additionally also have temperature distribution structures according to the following exemplary embodiments.

[0079] Represented in FIGS. 3A to 3D are exemplary embodiments for a substrate 6, on the surface 61 of which the first semiconductor layer can be grown. The substrate 6 is embodied as a growth substrate in the form of a wafer, having a diameter of, for example, greater or equal to 2 inches, and less than or equal to 12 inches. In particular, the wafer may have a diameter of 2 inches, or 4 inches, or 6 inches, or 8 inches, or 12 inches. Such a substrate 6 can be used to produce a multiplicity of semiconductor chips, by application of the semiconductor layer sequence and the further layers of the semiconductor chip on-wafer, and subsequent singulation. The substrate 6 may be used in a conventional coating process, in which one substrate or a plurality of such substrates is or are arranged on a suitable substrate carrier in a coating chamber.

[0080] As can be seen, for example, in FIGS. 3A and 3C, the substrate 6 has a temperature distribution structure 7, which can selectively produce an inhomogeneous lateral temperature distribution along at least one direction of extent of the first semiconductor layer to be grown. The temperature distribution structure 7 has temperature distribution structure elements 70, which are suitable and provided for influencing the local temperature distribution on the surface 61 during the growth process. These may be heat conducting elements, heating elements and/or thermal barrier elements, as described at a later point in conjunction with FIGS. 4A to 4K. According to the desired temperature-changing effect of the temperature distribution structure 7, the latter may have, or be composed of, a dielectric material, a semiconducting material, a metal, or a plurality or combination of these materials. Dielectric materials can effect, for example, local influencing of the thermal conductivity and thereby, as a result of an improved or reduced conduction of heat, a local raising or lowering of the temperature on the surface 61, and consequently in the growing first semiconductor layer. Semiconducting and metallic materials can likewise influence the thermal conductivity and/or be selectively heated by irradiation by light or other suitable electromagnetic radiation such as, for example, microwave radiation, such that, in the region of the temperature distribution structure elements 70, more heat is produced, and consequently a higher temperature can be generated than in the adjacent regions. As described above, for example in the case of InAlGaN, the indium content of the first semiconductor layer, which is highly dependent on the growth temperature, can thereby be set and varied. Accordingly, properties of the first semiconductor layer such as, for example, the refractive index, the band gap and consequently, if appropriate, the emission wavelength and the absorption behavior, can be varied laterally.

[0081] In particular, the temperature distribution structure 7 has a plurality of temperature distribution structure elements 70, which are arranged regularly and/or periodically in the lateral direction, according to the intended inhomogeneous lateral temperature distribution profile. As shown, the temperature distribution structure elements may be embodied, for example, in the form of mutually separate islands and/or line structures.

[0082] In the exemplary embodiment shown, the temperature distribution structure elements 70 have, along the direction of their arrangement, i.e. in the exemplary embodiment shown, in the lateral direction perpendicular to the direction of main extent of the linear structures, a lateral extent that is less than a corresponding lateral extent of the semiconductor chips to be produced, such that the local temperature change of each of the temperature distribution structure elements 70 can be produced, respectively, in a sub-region of a future semiconductor chip. Temperature distribution structure elements 70 whose width along the direction of arrangement is less than corresponding dimensions of the semiconductor chips makes it possible to produce, for example, the regions of the first semiconductor layer that are described in conjunction with FIGS. 2A to 2H.

[0083] FIGS. 3A to 3D show, purely exemplarily, for reasons of clarity, only three strip-type temperature distribution structure elements 70, which are located on a rear side of the substrate 6 that faces away from the surface 61. The lateral inhomogeneous temperature distribution resulting therefrom, which, in the case of InAlGaN, also corresponds to the indium distribution on the substrate 6, is indicated in FIG. 3B. Depending on the size of the substrate 6 and the size of the semiconductor chips to be produced, which, for example, as in the case of laser diode chips, may have lateral dimensions of less than 100 μm up to some 100 μm for single-emitter chips, and up to one or more centimeters for laser bars and laser arrays, the number of semiconductor chips produced on-wafer, and consequently also the number and dimensions of the temperature distribution structure elements 70, may vary considerably.

[0084] Owing to the clearly visible temperature distribution structure elements 70, the chip production process can be very precisely adjusted to the regions having a differing material composition. The temperature distribution structure elements 70 may be produced, for example, in any shape and arrangement by lithographic methods, rendering possible a material composition that is customized to the subsequent semiconductor chips, and consequently a corresponding variation of desired properties on the substrate 6.

[0085] As previously described, the temperature distribution structure 7 may preferably be arranged on the rear side of the substrate 6, which is opposite the surface 61 provided for the growth process, such that the growth process can proceed on the surface 61 without disturbance by the temperature distribution structure 7. As shown in FIGS. 3A and 3C, the temperature distribution structure 7 may be arranged directly on the rear side of the substrate. As an alternative to this, it is possible for the temperature distribution structure 7 to be covered by at least one protective layer, for example made of a dielectric material, or, as shown in FIG. 3D, to be embedded between two such protective layers 8, 9, in order to prevent the growth process from being affected by outgassing and/or vaporization of material from the temperature distribution structure 7. In the exemplary embodiment of FIG. 3D, a first protective layer 8 is arranged between the temperature distribution structure 7 and the substrate 6, while a second protective layer 9 covers the temperature distribution structure 7. The protective layers 8, 9 may have the same or differing materials.

[0086] Further features and exemplary embodiments relating to the temperature distribution structure 7 are described in FIGS. 4A to 4K, in which, in this case, respectively only a portion of the substrate 6 and semiconductor material 10 grown thereon, and consequently also of the temperature distribution structure 7 and of the temperature distribution structure elements 70, is shown. In particular, the temperature distribution structure 7 may have a plurality and/or a combination of the temperature distribution structure elements 70 described in the following. The temperature distribution structure elements 70 may have, in particular, a width in the lateral direction, which corresponds to a horizontal direction in the plane of the drawing, that is less than a width of the semiconductor chip to be produced above it. Furthermore, it is also possible for there to be a plurality of temperature distribution structure elements 70 in the region of a semiconductor chip, in order to produce a greater number of regions of differing material composition in the first semiconductor layer. The semiconductor material 10 may have, for example, one or more semiconductor layers grown on the substrate 6.

[0087] FIG. 4A shows a temperature distribution structure 7, having a temperature distribution structure element 70 that is arranged directly on the rear side of the substrate 6 that faces away from the surface 61. In particular, in the exemplary embodiment shown, the temperature distribution structure element 70 may have a different material than the substrate 6, and be embodied as a heating element that can be heated by being irradiated with suitable electromagnetic radiation, such that the substrate 6, and consequently also the semiconductor material 10 grown thereon, in the region over the temperature distribution structure element 70, can be heated to a higher temperature than in the adjacent regions that are not arranged over the temperature distribution structure element 70. For example, the temperature distribution structure element 70 shown may have a semiconducting material such as, for instance, silicon, which can be heated, for example, by irradiation of light having a wavelength that is in the absorption spectrum of the semiconducting material. As an alternative to this, the temperature distribution structure element 70 may also have, for example, a metal that can be heated by irradiation of suitable electromagnetic radiation such as, for example, microwave radiation.

[0088] During the growing of the semiconductor layer sequence, the substrate 6 may be supported, with the temperature distribution structure 7, on a substrate carrier, such that a conduction of heat between the substrate carrier and the substrate 6 can also simultaneously be influenced by the temperature distribution structure 7.

[0089] The substrate 6 may have, for example, a typical thickness in the range of from 100 μm to some 100 μm, for example 300 μm, such that the spread of heat in the lateral direction in the substrate 6 can be kept small in extent, and a desired temperature profile can be produced on the surface 61. Since the temperature distribution structure 7 is arranged on the rear side of the substrate 6, there is little chemical influence by the temperature distribution structure 7 during the growing of the semiconductor material 10. Depending on whether the substrate 6 remains, is thinned or removed entirely following the growing of the semiconductor material 10, the temperature distribution structure 7 can also remain in or be removed from the subsequently completed semiconductor chip. In particular, for example in the case of light-emitting diode chips, it is possible for the temperature distribution structure 7 to remain in the chip.

[0090] FIG. 4B shows an exemplary embodiment in which, in comparison with the previous exemplary embodiment, the temperature distribution structure 7 is arranged directly on the surface 61 of the substrate 6 that is provided for the process of growing the semiconductor material 10. The temperature distribution structure 7, which may be embodied, for example, as in the previous initial embodiment, is overgrown in the growing process by the semiconductor material 10, for example by means of a so-called ELOG process (ELOG: epitaxial lateral overgrowth). For this purpose, the temperature distribution structure 7 preferably has a thickness, in the direction of growth, of greater than or equal to 10 nm and less than or equal to 500 nm, or less than or equal to 300 nm, or less than or equal to 200 nm, or particularly preferably, less than or equal to 100 nm. As a result of the temperature distribution structure 7 being arranged on the surface 61 provided for growth, and consequently on the side of the substrate 6 that faces toward the semiconductor material 10, a spreading of heat in the substrate 6 can be avoided, thereby enabling a sharper temperature profile to be achieved. If, following the growing of the semiconductor layer sequence, the substrate 6 is not removed, or is only thinned, the temperature distribution structure 7 can remain in the subsequently completed semiconductor chip.

[0091] In order to protect the semiconductor material 10 against possible chemical impairment by the temperature distribution structure 7 and nevertheless avoid temperature spreading in the substrate 6, a protective layer 8 of a preferably dielectric material, for example an oxide, nitride or oxynitride, described above in the general part, which, together with the substrate 6, encapsulates the temperature distribution structure element 70, may be applied over the temperature distribution structure 7, as shown in FIG. 4C.

[0092] For example, the protective layer 8 may be applied by means of an application method such as, for instance, atomic layer deposition, that allows the formation of a layer that is as hermetically sealed as possible with, at the same time, a least possible layer thickness. The protective layer 8 in this case preferably does not extend over the entire surface 61 of the substrate 6, but insofar as possible covers only the elements of the temperature distribution structure 7.

[0093] Shown in FIG. 4D is a further exemplary embodiment, in which the temperature distribution structure 7, which is arranged on the rear side of the substrate 6 and which may be embodied as in FIG. 4A, is likewise covered by a protective layer 8, as described in conjunction with FIG. 4C. The protective layer 8 in this case may cover the entire rear side of the substrate 6 or also, as an alternative to the exemplary embodiment shown, only the temperature distribution structure element 70. Apart from avoidance of chemical influencing of the growth process, a suitable protective layer 8 may also be used, for example, to avoid a possible undesired attachment or adhesion to the substrate carrier.

[0094] As shown in FIG. 4E, the temperature distribution structure element 70 may also be surrounded on all sides by a protective layer 8, and thus embedded in the latter. In this case, the temperature distribution structure 7 is not directly arranged on the substrate 6. Instead of the design shown, of an embedded protective layer 8, as an alternative to this it is also possible, as described above in conjunction with FIG. 3D, for two protective layers to be used, between which the temperature distribution structure element 70 is arranged.

[0095] As shown in conjunction with FIGS. 4F and 4G, the temperature distribution structure 7 may also be embedded in the semiconductor material 10 or in the substrate 6. For this purpose, particularly preferably, a semiconductor material having a small band gap may be used to produce corresponding temperature distribution structure elements 70 embodied as heating elements. As an alternative to this, the temperature distribution structure 7 may also have a thermal conductivity that differs from that of the surrounding substrate material 6 or semiconductor material 10, such that the temperature distribution structure element 70 may be embodied as a heat conducting element or thermal barrier element integrated into the substrate 6 or into the semiconductor material 10. The temperature distribution structures 7 shown in FIGS.4F and 4G may be produced, for example, by implantation. Furthermore, it is also possible for the substrate 6, or the semiconductor material 10 together with the substrate 6, to form a quasi-substrate having over-grown temperature distribution structures 7 and a subsequently planarized surface.

[0096] Shown in conjunction with FIGS. 4H to 4K are temperature distribution structures 7 having temperature distribution structure elements 70, which have, or are composed of, one or more elevations and/or recesses. For example, a surface structure having elevations and recesses that form the temperature distribution structure elements 70 may be formed in the rear side of the substrate 6 that faces away from the surface 61. Since the substrate 6 sits only with the elevations on a substrate carrier, the temperature coupling there is better, and consequently the temperature is locally higher in the regions over the elevations than in the regions over the adjacently arranged recesses. A differing thermal coupling of the substrate 6 to the substrate carrier is thus made possible. In this case, the temperature distribution structure elements 70 embodied as elevations may have the same material as the substrate 6 and, particularly preferably, be formed in one piece with the substrate 6.

[0097] As shown in FIG. 4I, the elevations and recesses formed by the temperature distribution structure 7 may also be composed of a material that is different from the substrate 6.

[0098] Shown in FIG. 4J is a temperature distribution structure 7 that is a combination of the temperature distribution structures 7 described in conjunction with FIGS. 4A and 4H. On the one hand, a temperature distribution structure element 70 that is embodied as a heating element is arranged on the rear side of the substrate. Additionally provided, in the rear side of the substrate, are temperature distribution structure elements 70 embodied as depressions, which form separating grooves that act as thermal barriers, whereby thermal spread in the substrate 6 can be reduced and a sharper temperature profile can thus be created.

[0099] As shown in FIG. 4K, a material having a lesser thermal conductivity than the substrate 6 may additionally be arranged in the recesses on the rear side of the substrate, in order to increase the thermal barrier function of the thus formed temperature distribution structure elements 70.

[0100] Indicated schematically in FIG. 5A is a typical temperature profile on the surface 61 of a wafer that can be used as a substrate 6 for the method describe here, in a conventional substrate carrier. It can be seen that the temperature distribution is not homogeneous over the substrate surface 61, but varies on a length scale and in lateral directions that depend on the arrangement of the semiconductor chips to be produced on-wafer. A corresponding temperature distribution may also be present, for example, in the growing of the first semiconductor layer. As previously described, this temperature profile affects the material composition of the semiconductor layers of the semiconductor chips, such that the semiconductor chips produced on-wafer may have mutually differing properties. In order to avoid this, the temperature profile on the surface 61 provided for the growth process may be homogenized in an additional method step, as shown in FIG. 5B and, on the basis thereof, as shown in FIG. 5C, set according to the desired inhomogeneous lateral temperature distribution.

[0101] As shown in the exemplary embodiments according to the following FIGS. 6A to 6F, in usual coating installations usually a plurality of substrates 6 are arranged on a substrate carrier 200, to enable these substrates to be coated simultaneously. In order to achieve a coating that is as homogeneous as possible, the substrate carrier 200 rotates, as shown by the arrow indicating the rotation direction 201. By means of the substrate carrier 200, the substrates 6 are heated to the desired growth temperature, and there may be inhomogeneous temperature distributions, such as that shown exemplarily in FIG. 5A, present on the surfaces 61. In order to homogenize the respective temperature profile on the surface 61 of the substrate 6, which profile may be different for each substrate 6, this can first be measured, for example by means of an infrared detector.

[0102] Furthermore, each of the substrates 6 is selectively heated in sub-regions, in order to create, on the respective surface 61 thereof, a temperature profile that is as homogeneous as possible. Such heating may be effected, for example, as shown in FIG. 6A, by means of a locally varying light radiation, i.e. by means of irradiation of a suitably variable light beam 300, which can be absorbed, for example, in the substrate material or a semiconductor material applied to the substrates 6. The light beam may be, for example, a single beam or multiple beam of one or more light sources, and be selectively deflected onto selected sub-regions of the surfaces 61 of the substrates 6 by means of a suitable light deflecting means 400, for instance by means of a mirror or another suitable device. As an alternative to this, as shown in FIG. 6B, it is also possible to use, for example, a plurality of light sources 301, for example a plurality of laser sources in a laser array, which preferably can irradiate light independently of one another onto the surface 61 of a substrate 6. Preferably, the entire surface 61 of the substrates 6 can thereby be covered in each case, the light irradiation being effected with the rotary motion of the substrate carrier 200 and the determined individual temperature profiles of the substrates 6 being taken into account.

[0103] The inhomogeneous lateral temperature distribution desired for growing the first semiconductor layer may be created by means of a previously described temperature distribution structure that is additionally present. As an alternative to this, it is also possible for this to be produced, likewise, by means of the described light irradiation, the heating profile to be effected by the light irradiation being adapted accordingly, in comparison with a pure homogenization of the temperature profile. Moreover, it is also possible for the light heating formed by a locally varying light irradiation to be used, without an additional homogenization step, only to create a desired inhomogeneous temperature profile.

[0104] As previously described, the locally varying light irradiation during the growing of the first semiconductor layer may comprise irradiation by means of a laser, which radiates onto the growing first semiconductor layer, in predefined and specifically selected regions, one or more light beams 300, which, as a result of absorption in the growing first semiconductor layer or in a layer underneath, such as, for example, an already grown layer and/or the substrate 6, results in a local and inhomogeneous heating in these regions, such that differing effective growth temperatures prevail in differing regions for the growing first semiconductor layer. The locally varying light irradiation may be realized, in particular, such that one or more regions, whose surface extents are less than those of the semiconductor chips, can be irradiated simultaneously or successively on the substrate 6. The light irradiation in this case may also be effected in a pulsed manner. Scanning of the surface on which the first semiconductor layer is grown is made possible by the described light deflecting means 400 and/or by the use of a plurality of light sources 301.

[0105] As shown in FIGS. 6A to 6F, the substrates 6 or, alternatively, also the substrate carrier 200 may be formed with at least two markings 62, which serve as reflectors, or adjustment marks, to enable the light beam 300 to be synchronized. As shown exemplarily in FIGS. 6C and 6D, at an instant T1, for example, the light beam 300 denoted by A may strike a marking 62 and be reflected by the latter (FIG. 6C) while, at the same or a later instant T2, the light beam 300 denoted by B strikes a marking 62 and is reflected by the latter (FIG. 6D). The reflected signals from the markings 62 can be used, on the one hand, to enable an exact synchronization of the light beam 300 onto the substrate 6. In addition, it is possible to calculate a rotation of the substrate 6 in the substrate carrier 200 on the basis of the possibly time-delayed signals from the at least two markings 62, and thus to adjust the required temperature profile to correspond to the markings 62. The markings 62 may be used both in a homogenization of the temperature profile and subsequently in the chip process, for adjusting the chip structures to correspond to the temperature profile.

[0106] It is also possible to use a plurality of light sources, in the form of a plurality of individual light sources or, as shown in FIG. 6B, in the form of several pluralities of light sources 301, for the purpose of simultaneously heating a plurality of substrates 6. It is thereby possible to achieve a more uniform temperature distribution during the rotation of the substrate carrier 200. Moreover, more power can be applied locally, since a plurality of light sources can illuminate one same region on a substrate 6, such that greater temperature gradients are possible. Furthermore, the local resolution can also be improved by an offset arrangement, for example of a plurality of laser arrays constituted by a plurality of light sources 301.

[0107] As shown in FIG. 6F, the pluralities of light sources 301 may also illuminate only sub-regions of the substrates 6. This makes it possible, for example, to simplify the assignment of reflected signals from the markings 62. Furthermore, detectors 500 may be arranged on the substrate carrier 200 or in the proximity thereof, to enable direct detection of the signals reflected by the markings 62.

[0108] The exemplary embodiments and the features thereof that are described in conjunction with the figures may be combined with one another, according to further exemplary embodiments, even if such combinations are not explicitly described. Furthermore, the exemplary embodiments described in conjunction with the figures may have alternative and additional features, according to the description in the general part.

[0109] The description on the basis of the exemplary embodiments does not limit the invention to these exemplary embodiments. Rather, the invention comprises each new feature and each combination of features, this including, in particular, each combination of features in the claims, even if this feature, or this combination itself, is not explicitly stated in the claims or exemplary embodiments.

LIST OF REFERENCES

[0110] 1 first semiconductor layer [0111] 2 second semiconductor layer [0112] 3 third layer [0113] 4 contact layer [0114] 5 passivation layer [0115] 6 substrate [0116] 7 temperature distribution structure [0117] 8, 9 protective layer [0118] 10 semiconductor material [0119] 11, 12, 13, 14 region [0120] 21 ridge waveguide structure [0121] 61 surface [0122] 62 marking [0123] 70 temperature distribution structure element [0124] 100 semiconductor chip [0125] 200 carrier [0126] 201 rotation direction [0127] 300 light beam [0128] 301 plurality of light sources [0129] 400 light deflecting means [0130] 500 detector [0131] 1000, 2000, 3000 method step