Methods for forming tungsten gap fill on a feature. A method for forming tungsten gap fill in a feature can include: treating a first layer on a substrate having a portion of the first layer exposed through the feature; depositing a tungsten liner layer atop the treated portion of the first layer in the feature using a physical vapor deposition (PVD) process; and depositing a tungsten fill layer into the feature and atop the tungsten liner layer using a chemical vapor deposition (CVD) process.

Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.

A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.