An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

Methods and systems for forming a structure including multiple carbon layers and structures formed using the method or system are disclosed. Exemplary methods include forming a first carbon layer and a second carbon layer, wherein a density and/or other property of the first carbon layer differs from the corresponding property of the second carbon layer.

In this work is presented a method for fabrication of high-aspect ratio structures through spalling effect. The spalling is achieved through lithography, etching and sputtering processes, thus providing the flexibility to position the spalled structures according to the application requirements. This method has been successfully demonstrated for metal-oxides and metals. The width of the fabricated structures is dependent on the thickness of the film deposited by sputtering, where structures as small as 20 nm in width have been obtained.

The method for forming overlay marks includes: providing a substrate, a surface of the substrate having a mark layer and a first mask layer; forming first trenches and second trenches in the first mask layer; forming a spacer layer covering side walls of the first trenches and side walls of the second trenches; backfilling the first trenches and the second trenches; removing the spacer layer; and etching the mark layer and forming main overlay marks and dummy overlay marks.

A pattern formation method includes: forming a photosensitive hard mask made of a transition metal oxide film on a surface of a substrate; exposing the photosensitive hard mask to EUV light in a desired pattern; causing a state change in an exposed region by heat generated during exposure; and selectively removing either a region where the state change has occurred or a region where the state change has not occurred.

A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

A semiconductor structure and a method for preparing a semiconductor structure are provided. The method includes: a composite hard mask layer is formed on an etching layer, the composite hard mask layer including a hard mask layer and an etching stop layer surrounded by the hard mask layer; a first target pattern and a first redundant pattern are formed in the composite hard mask layer; a remaining part of the etching stop layer is removed to form a second target pattern and a second redundant pattern in the hard mask layer; etching is performed by using the second target pattern and the second redundant pattern as masks to form a target structure in the etching layer and to form a redundant structure in the hard mask layer; and a remaining part of the hard mask layer is removed.

A method for forming a semiconductor structure includes forming a hard mask layer over a target layer. The method also includes forming first mandrels over the hard mask layer. The method also includes forming a first opening in the first mandrels. The method also includes depositing a spacer layer over the hard mask layer and the first mandrels. The method also includes depositing a second mandrel material over the spacer layer. The method also includes planarizing the second mandrel material. The method also includes forming a second opening in the second mandrel material. The method also includes patterning and etching the second mandrel material to form second mandrels. The method also includes etching the spacer layer. The method also includes etching the hard mask layer and the target layer.

A hard mask-forming composition which forms a hard mask used in lithography, including: a resin containing an aromatic ring and a polar group; and a compound containing at least one of an oxazine ring fused to an aromatic ring, and a fluorene ring.