Method for manufacturing an electronic device, comprising the steps of: forming, at a front side of a solid body of 4H-SiC having a first electrical conductivity, at least one implanted region having a second electrical conductivity opposite to the first electrical conductivity; forming, on the front side, a 3C-SiC layer; and forming, in the 3C-SiC layer, an ohmic contact region which extends through the entire thickness of the 3C-SiC layer, up to reaching the implanted region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method for producing microcracks in an interior of a composite structure includes: providing or producing the composite structure which has a solid body and at least one metallic coating and/or electrical components situated or provided on one side of the solid body, the solid body containing or being made of silicon carbide (SiC); and producing modifications in the interior of the solid body. Laser radiation is introduced into a flat surface of the solid body to cause multiphoton excitation which brings about plasma generation. The modifications are effected by the plasma in the form of a material transformation which generates compressive stresses in the solid body, thereby developing subcritical cracks in a surrounding area of a particular modification. The laser radiation is introduced into the solid body in pulses having an intensity which reaches a maximum within 10 ns after a start of a particular pulse.

A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm.sup.2 to 20,000 ea/cm.sup.2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

The present application relates to a method for preparing a polishing slurry, the method including the steps of preparing a solution containing abrasive particles and a fluid, passing the solution through a porous membrane filter region, and preparing a polishing slurry by removing the fluid from the solution that has passed through the region, in which in the step of passing the solution through the region, those with a mean particle size of 100 nm or less among the abrasive particles are removed by a tangential flow filtration method.

The technology of this application relates to a silicon carbide substrate, a silicon carbide device, and a substrate thinning method thereof. The method includes: providing a first substrate, where the first substrate is a silicon carbide substrate, and the first substrate has a silicon surface and a carbon surface that are opposite to each other; forming a silicon carbide device on the silicon surface of the first substrate, and forming a protective layer on the silicon carbide device; performing ion implantation on the carbon surface of the first substrate; providing a second substrate; bonding an ion-implanted first substrate to the second substrate; performing high-temperature annealing on the bonded first substrate and the second substrate to combine ions implanted into the first substrate into gas; and performing separation at a position of ion implantation of the first substrate to obtain a thinned first substrate and a separated first substrate.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.