Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.

Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.

A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding.

A bonding system includes a surface modifying apparatus configured to modify a bonding surface of a first substrate and a bonding surface of a second substrate; a surface hydrophilizing apparatus configured to hydrophilize the modified bonding surface of the first substrate and the modified bonding surface of the second substrate; a bonding apparatus configured to perform bonding of the hydrophilized bonding surface of the first substrate and the hydrophilized bonding surface of the second substrate in a state that the bonding surfaces face each other; and a cleaning apparatus configured to clean, before the bonding is performed, a non-bonding surface of, between the first substrate and the second substrate, at least one which is maintained flat when the bonding is performed, the not-bonding surface being opposite to the bonding surface.

A process for fabricating a growth substrate comprises preparing a donor substrate by forming a crystalline semiconductor surface layer on a seed layer of a carrier. This preparation comprises forming the surface layer as a plurality of alternations of an InGaN primary layer and of an AlGaN secondary layer, the indium concentration and the thickness of the primary layers and the aluminum concentration and the thickness of the secondary layers being selected so that a homogeneous AlInGaN layer that is equivalent, in terms of concentration of aluminum and indium-, to the surface layer has a natural lattice parameter different from the lattice parameter of the seed layer.

A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.

A semiconductor structure is provided that includes a silicon germanium alloy fin located on a portion of a topmost surface of an insulator layer. A functional gate structure straddles a portion of the silicon germanium alloy fin and is located on other portions of the topmost surface of the insulator layer. A source structure is located on one side of the functional gate structure and a drain structure is located on another side of the functional gate structure. The source structure and the drain structure surround the other portions of the silicon germanium alloy fin and are located on a germanium graded silicon-containing region that is present at a footprint of the other portions of the silicon germanium alloy fin.