The present invention provides a mounting apparatus, including a bonding stage holding a substrate on which a semiconductor chip is arranged; a base stand; a mounting head mounted with a pressing tool that presses the semiconductor chip on the substrate; and a film arranging mechanism provided on the base stand and moving a cover film along the bonding stage to arrange the cover film between the semiconductor chip pressed by the substrate and the pressing tool. The film arranging mechanism includes film guides guiding the cover film and defining a height with respect to the bonding stage; and lifting mechanisms connected to the film guides via springs and lifting and lowering the film guides with respect to the bonding stage.

The present invention provides a mounting apparatus and a parallelism detection method in the mounting apparatus. The parallelism detection method in the mounting apparatus includes: a first height detection process of detecting first heights of a mounting tool when a holding surface comes into contact with the a tip of a triangular pin by placing the triangular pin on a placement surface of a stage and lowering the mounting tool; a second height detection process of detecting second heights of the mounting tool when the tip of the triangular pin comes into contact with the placement surface by holding the triangular pin on the holding surface of the mounting tool and lowering the mounting tool; and a parallelism calculation process of calculating the parallelism between the placement surface of the stage and the holding surface of the mounting tool based on the first heights and the second heights.

Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.