The present invention relates to a joined component formed by friction stir welding and, more particularly, to a joined component formed in a structure in which no interface exists between flow paths formed therein.

According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a first surface, a second surface crossing the first surface, and an edge portion connecting the first surface and the second surface. The particle-resistant layer includes a polycrystalline ceramic and covering the first surface, the second surface, and the edge portion. The particle-resistant layer includes a first particle-resistant layer provided at the edge portion, and a second particle-resistant layer provided at the first surface. A particle resistance of the first particle-resistant layer is higher than a particle resistance of the second particle-resistant layer.

According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a main portion and an alumite layer. The main portion includes aluminum. The alumite layer is provided at a front surface of the main portion. The particle-resistant layer is provided on the alumite layer and includes a polycrystalline ceramic. A Young's modulus of the alumite layer is greater than 90 GPa.

Replaceable contact pads of end effectors are provided. The contact pads support substrates in electronic device manufacturing. The contact pad includes a contact pad head having a contact surface configured to contact a substrate, a shaft coupled to the contact pad head, the shaft including a shaft indent formed between an underside of the contact pad head and a shaft end, and a circular securing member received around the shaft and seated in the shaft indent and configured to secure the contact pad to the end effector body. End effectors including replaceable contact pads and maintenance methods are described, as are additional aspects.

Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus described herein include a chamber body defining a processing volume. In one embodiment, a major axis of the processing volume is oriented vertically and a minor axis of the processing volume is oriented horizontally. One or more electrodes may be disposed adjacent the processing volume and at least partially define the processing volume. Process fluid is provided to the processing volume via a plurality of fluid conduits to facilitate immersion field guided post exposure bake processes. A plurality of seals maintains the fluid containment integrity of the processing volume during processing. A post process chamber for rinsing, developing, and drying a substrate is also provided.

A mask material is readily discernible from a substrate to which the mask material is applied. The mask material may have a discernible characteristic, such as its color, luminescence or the like, which may render it visibly distinct from the substrate or detectable using automated inspection equipment. The discernible characteristic of the mask material may render it detectable through a protective coating.

The present disclosure relates to high pressure processing apparatus for semiconductor processing. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber.

A screen plate, a packaging method, a display panel and a display device are provided. The screen plate includes a frame, a mesh fixed onto the frame and a masking film arranged on the mesh. A printing area is formed in a portion of the mesh that is not masked by the masking film. At least one masking line is arranged in the printing area. The at least one masking line is arranged along an edge of the masking film respectively. A width of the masking line is greater than a width of each mesh line of the mesh.

A cleaning wafer or substrate for use in cleaning, or in combination with, components of, for example, integrated chip manufacturing apparatus. The cleaning substrate can include a substrate having varying predetermined surface features, such as one or more predetermined adhesive, non-tacky, electrostatic, projection, depression, or other physical sections. The predetermined features can provide for more effective cleaning of the components with which they are used, such as an integrated chip manufacturing apparatus in the place of the integrated chip wafer. The cleaning substrate can be urged into cleaning or other position by vacuum, mechanical, electrostatic, or other forces. The cleaning substrate can adapted to accomplish a variety of functions, including abrading or polishing. The cleaning substrate may be made by a novel method of making, and it may then be used in a novel method of use I combination with chip manufacturing apparatus.

Briefly, in accordance with one embodiment, a transparent conductive structure and method to form such a structure are described. For example, an apparatus may include an optoelectronic device. In such an embodiment, an optoelectronic device may include one or more zinc oxide crystals forming a single contiguous three-dimensional transparent conductive structure. The single contiguous three-dimensional transparent conductive structure may include one or more regions thereof having one or more three dimensional geometrical features in the one or more regions of the single contiguous three-dimensional transparent conductive structure so that the single contiguous three-dimensional transparent conductive structure possesses additional electrical-type and/or optical-type properties. For example, additional electrical-type and/or optical-type properties may include electrical current management and/or light management properties.