Provided are a heat dissipation structure, a method for forming a heat dissipation structure, and a semiconductor structure. The heat dissipation structure includes a first heat dissipation ring and a second heat dissipation ring. The first heat dissipation ring is formed in a dielectric layer around a Through Silicon Via (TSV) and in contact with the TSV. The TSV passes through a silicon substrate and the dielectric layer. The second heat dissipation ring is formed around the first heat dissipation ring, and in contact with the first heat dissipation ring. The second heat dissipation ring has a heat dissipation gap within it. A dimension of the second heat dissipation ring in a first direction is less than that of the first heat dissipation ring in the first direction. The first direction is a thickness direction of the silicon substrate.

The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

A method for forming a semiconductor structure includes the following operations. A substrate is provided, and the substrate includes an active surface and a back surface opposite to the active surface. An etching stop layer is formed on the back surface of the substrate. The substrate is fixed onto a first temporary carrier to make the etching stop layer be located between the substrate and the first temporary carrier. The substrate is etched until reaching the etching stop layer to form a via structure penetrating through the substrate.

A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.

Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

There is provided a technique that includes (a) supplying a first-element-containing gas to the substrate; (b) supplying a first reducing gas to the substrate; (c) supplying a second reducing gas, which is different from the first reducing gas, to the substrate; (d) supplying a third reducing gas, which is different from both the first reducing gas and the second reducing gas, to the substrate; (e) after a start of (a), performing (b) in parallel with (a); (f) in (e), performing (d) in parallel with (b); and (g) forming a first-element-containing film on the substrate by alternately performing (e) and (c) a predetermined number of times.

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.

The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

A substrate dividing method includes preparing a substrate that is formed with division start points along streets and that has a protective sheet attached to a surface on one side thereof and rolling a roller on a surface on the other side of the substrate, to attach an expanding tape. Next, suction by a holding table is cancelled, and, in a state in which a slight gap is formed between a holding surface of the holding table and the protective sheet, the roller is brought into contact with the expanding tape and rolled, thereby extending cracks extending from the division start points while causing the substrate to sink into the gap through the protective sheet with the division start points as starting points, and the expanding tape is expanded to widen the chip intervals with the division start points as starting points.