A method of manufacturing an active array substrate, comprising: providing a substrate; forming gate electrodes on the substrate; forming a gate insulating layer, a semiconductor layer and an Ohmic contact layer on the transparent substrate and the gate electrodes in order; forming source electrodes and drain electrodes on the Ohmic contact layer; forming a protection layer on the source electrodes and the drain electrodes; and forming a pixel electrode layer on the protection layer, wherein the pixel electrode layer is electrically connected to the drain electrode. The gate insulating layer comprises nanometer porous silicon and nanometer particles, and a dielectric constant of the nanometer particle is greater than a dielectric constant of the nanometer porous silicon.

A control method for differentiated etching depth is provided. The method includes: providing a first etching stop pattern layer in a panel having stacked structure; adopting a first etchant to perform a first etching process to the panel such that a location of the panel provided with the first etching stop pattern layer forms a first etching depth, and forms a second etching depth at a location of the panel without providing the first etching stop pattern layer; through controlling an etching time, the second etching depth is deeper than a bottom of the first etching stop pattern layer; and adopting a second etchant to perform a second etching process to the panel in order to etch and remove the first etching stop pattern layer. In a same mask process, through changing the etchant, different depths are etched and formed to reduce the time consuming and decrease the production cost.

The method for manufacturing a thin film transistor includes sequentially forming a gate electrode on a surface of a substrate, forming a gate insulating layer covering the surface of the substrate and the gate electrode, forming an active layer and an etching stop layer above the gate electrode, forming a metal layer including a first region covering the etching stop layer and a pair of second regions connecting both sides of the first region on the active layer, and forming a photosensitive layer on the metal layer; removing a portion of the photosensitive layer to expose a portion of the first region; removing the exposed portion of the first region with the remaining first region having a height same as the remaining photosensitive layer located at two opposite sides of the etching stop layer; and removing the remaining photosensitive layer.

The present disclosure provides a TFT substrate and a manufacturing method thereof and a manufacturing method of an OLED panel. In the manufacturing method of the TFT substrate of the present disclosure, firstly formed a first inter layer dielectric covering the gate and the active layer on the buffer layer, wherein material of the first inter layer dielectric is provided as silicon oxynitride; Further, forming a second inter layer dielectric on the first inter layer dielectric, wherein material of the second inter layer dielectric is provided as silicon oxide, which can prevent excessive hydrogen elements from being introduced into the active layer, improve the working stability of the TFT device. The TFT substrate of the present disclosure is manufactured by using the above manufacturing method of a TFT substrate, the gate and the active layer have stable performance, and the TFT device has better working stability.

A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes; a base substrate; pixel units on the base substrate, each pixel unit including a drive circuit layer; and a patterned metal layer between the drive circuit layer and the base substrate the metal layer including a first part at least configured to be connected with a power line of the drive circuit layer.

A method for manufacturing an array substrate includes forming a buffer layer on a substrate; forming a source and a data line in the buffer layer, forming a first gate, a second gate, a first scan line, and a second scan line on the buffer layer, simultaneously; forming a semiconductor layer; forming a conductor layer by converting the semiconductor layer formed on the first scan line and the second scan line into a conductor; forming a first pixel electrode on the semiconductor layer and forming a second pixel electrode on the conductor layer, simultaneously.

Provided is a method of manufacturing an electronic device, the method including: preparing first mother glass and second mother glass; forming, on the first mother glass, a plurality of device cells partially connected to the first mother glass through a plurality of first separating portions; patterning a device circuit on each of the plurality of device cells; forming, on the second mother glass, a plurality of cover cells partially connected to the second mother glass through a plurality of second separating portions; forming a plurality of electronic devices by laminating the first mother glass and the second mother glass together such that the plurality of device cells are respectively aligned to the plurality of cover cells; and separating the plurality of electronic devices from the first mother glass and the second mother glass by cutting the plurality of first separating portions and the plurality of second separating portions.

The present disclosure provides an array substrate and a display device. The array substrate includes: first common electrode lines; gate lines; a gate insulation layer; data lines, the first common electrode lines crossing the data lines to define a plurality of pixel units, each gate line dividing a corresponding pixel unit into two sub-regions, a separate TFT being arranged at each sub-region; second common electrode lines; and a drain electrode pad arranged at each sub-region and a drain electrode connection line for connecting the drain electrode pad to a drain electrode of the TFT. The drain electrode pad, the drain electrode connection line and the drain electrode are arranged at an identical layer. An orthogonal projection of each second common electrode line onto the base substrate overlaps an orthogonal projection of the drain electrode pad onto the base substrate.

An array substrate, a manufacturing method thereof and a display device. The array substrate includes a substrate, a thin film transistor on the substrate, and including an active layer including a source region, a drain region and a channel region between the source region and the drain region; a heat dissipation layer disposed between the substrate and the drain region; and the orthographic projection of the heat dissipation layer on the substrate at least covers the orthographic projection of a part of the source region and a part of the drain region on the substrate. The manufacturing method is for the manufacturing of the array substrate. The array substrate can improve the sizes and uniformity of the crystal particles.

The present invention provides a method and a device for releasing film layer stress of an array substrate. In the method for releasing film layer stress of an array substrate, the array substrate is positioned, in a still condition, on a carrying table involving an arc surface and a carrying table curvature adjusting mechanism is operated to gradually vary the curvature of the arc surface of the carrying table such that the array substrate, under the action of the gravity, is caused to curve according to the arc surface of the carrying table and the degree of curving varies following the variation of the curvature of the arc surface of the carrying table so as to make each film layer of the array substrate exhibiting uniform tension stress or compression stress, and eventually, the stress accumulated among the film layers of the array substrate during a manufacturing process can be released through the action of the external force, thereby reducing the influence that an external pressure causes on the property of a device provided on the array substrate during a subsequent process and uses thereof, so as to reduce poor displaying of a display panel and ensure product yield.