An electronic component includes an insulating surrounding member surrounding the electronic element while allowing a first surface of the electronic element to be exposed from a second surface of the surrounding member. A wiring board faces a third surface comprising the first and second surfaces. An insulating joining member is interposed between the third surface and the wiring board and joins the third surface and the wiring board together. A conductive bump, located between the third surface and the wiring board, electrically connects the electronic element and the wiring board. The joining member has a first through hole that overlaps a vibration region in the first surface in perspective plan view. The joining member has a second through hole that accommodates the bump. At least a portion of at least one of the first through hole or the second through hole overlaps the second surface in perspective plan view.

An electronic component includes an insulating surrounding member surrounding the electronic element while allowing a first surface of the electronic element to be exposed from a second surface of the surrounding member. A wiring board faces a third surface comprising the first and second surfaces. An insulating joining member is interposed between the third surface and the wiring board and joins the third surface and the wiring board together. A conductive bump, located between the third surface and the wiring board, electrically connects the electronic element and the wiring board. The joining member has a first through hole that overlaps a vibration region in the first surface in perspective plan view. The joining member has a second through hole that accommodates the bump. At least a portion of at least one of the first through hole or the second through hole overlaps the second surface in perspective plan view.

A package structure comprises a metal plate (20) where a slot is formed, a ceramic piece (60), and a metal heat sink (70) welded onto the back surface of the ceramic piece (60). The ceramic piece (60) and the metal heat sink (70) are vertically inserted into the slot and welded to the metal plate (20). A semiconductor and a matching circuit may be disposed on the metal heat sink (70). The ceramic piece (60) replaces a glass seal; metalized interconnection is provided inside the ceramic piece (60) for fabricating a metalized pattern having complex connection relations, and the electrical interconnection is more flexible. In the package structure, metalized wiring is carried out by using the ceramic piece. Compared with round lead machining, higher precision is achieved.

A package structure comprises a metal plate (20) where a slot is formed, a ceramic piece (60), and a metal heat sink (70) welded onto the back surface of the ceramic piece (60). The ceramic piece (60) and the metal heat sink (70) are vertically inserted into the slot and welded to the metal plate (20). A semiconductor and a matching circuit may be disposed on the metal heat sink (70). The ceramic piece (60) replaces a glass seal; metalized interconnection is provided inside the ceramic piece (60) for fabricating a metalized pattern having complex connection relations, and the electrical interconnection is more flexible. In the package structure, metalized wiring is carried out by using the ceramic piece. Compared with round lead machining, higher precision is achieved.

Wafer level encapsulated packages includes a wafer, a glass substrate hermetically sealed to the wafer, and an electronic component. The glass substrate includes a glass cladding layer fused to a glass core layer and a cavity formed in the glass substrate. The electronic component is encapsulated within the cavity. In various embodiments, the floor of the cavity is planar and substantially parallel to a plane defined by a top surface of the glass cladding layer. The glass cladding layer has a higher etch rate in an etchant than the glass core layer. In various embodiments, the wafer level encapsulated package is substantially optically transparent. Methods for forming the wafer level encapsulated package and electronic devices formed from the wafer level encapsulated package are also described.

Wafer level encapsulated packages includes a wafer, a glass substrate hermetically sealed to the wafer, and an electronic component. The glass substrate includes a glass cladding layer fused to a glass core layer and a cavity formed in the glass substrate. The electronic component is encapsulated within the cavity. In various embodiments, the floor of the cavity is planar and substantially parallel to a plane defined by a top surface of the glass cladding layer. The glass cladding layer has a higher etch rate in an etchant than the glass core layer. In various embodiments, the wafer level encapsulated package is substantially optically transparent. Methods for forming the wafer level encapsulated package and electronic devices formed from the wafer level encapsulated package are also described.

A method for manufacturing a ceramic substrate that includes preparing a plurality of ceramic green sheets, at least one of the plurality of ceramic green sheets having a disappearance material that disappears by firing in a recessed portion formation planned region of the at least one of the plurality of ceramic green sheets; forming a mother multilayer body by laminating the plurality of ceramic green sheets such that the at least the one ceramic green sheet having the disappearance material is positioned on an uppermost layer of the mother multilayer body; and forming a recessed portion in the mother multilayer body before firing by pressing the recessed portion formation planned region of the mother multilayer body.

A method for manufacturing a ceramic substrate that includes forming a mother multilayer body by positioning a hole in at least one ceramic green sheet among a plurality of laminated ceramic green sheets in a location that does not overlap with a recess formation-planned region in which a recess is to be formed after firing of the mother multilayer body and that overlaps with a singulation-planned line for singulating the mother multilayer body into pieces after firing; and forming the recess in the mother multilayer body before firing by performing press working on the recess formation-planned region of the mother multilayer body.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.