An implantable device and method of manufacture include a substantially hermetic polychlorotrifluoroethylene (PCTFE) enclosure with closely-spaced wires extending out of the enclosure. The implantable device includes a PCTFE first portion of an enclosure and a PCTFE second portion of the enclosure. The first and second portions are configured to mate with each other to form the enclosure. A plurality of insulated wires extend between the first and second portions of the enclosure. Each of the insulated wires are parallel to each other and separated by less than 150 micrometers (μm) from a neighboring wire. A thermal weld seam of PCTFE is disposed between the first portion of the enclosure and the second portion of the enclosure and conformally adheres around insulation of each wire such that the enclosure is sealed.

An implantable device and method of manufacture include a substantially hermetic polychlorotrifluoroethylene (PCTFE) enclosure with closely-spaced wires extending out of the enclosure. The implantable device includes a PCTFE first portion of an enclosure and a PCTFE second portion of the enclosure. The first and second portions are configured to mate with each other to form the enclosure. A plurality of insulated wires extend between the first and second portions of the enclosure. Each of the insulated wires are parallel to each other and separated by less than 150 micrometers (μm) from a neighboring wire. A thermal weld seam of PCTFE is disposed between the first portion of the enclosure and the second portion of the enclosure and conformally adheres around insulation of each wire such that the enclosure is sealed.

A semiconductor device includes: a plate-shaped terminal including one main surface and another main surface and having one end electrically connected to a semiconductor chip; a nut arranged on the one main surface side at another end of the terminal; a nut cover provided on the one main surface side at the other end of the terminal and configured to cover the nut; and a case configured to surround the semiconductor chip and integrate the terminal and the nut cover, wherein the nut cover includes a protruding portion protruding from a lower portion of the nut cover to the one end side of the terminal.

A semiconductor device includes: a plate-shaped terminal including one main surface and another main surface and having one end electrically connected to a semiconductor chip; a nut arranged on the one main surface side at another end of the terminal; a nut cover provided on the one main surface side at the other end of the terminal and configured to cover the nut; and a case configured to surround the semiconductor chip and integrate the terminal and the nut cover, wherein the nut cover includes a protruding portion protruding from a lower portion of the nut cover to the one end side of the terminal.

A ceramic substrate is mainly constituted of ceramic, and has a first main surface and a second main surface located opposite to the first main surface. A recessed portion recessed toward a first main surface side is formed in the second main surface. A wire portion extending from an outer peripheral surface of the ceramic substrate to inside of the recessed portion is formed, and a bottom portion located on the first main surface side in the recessed portion has a portion thinner than another portion of the ceramic substrate other than the bottom portion.

A quartz crystal resonator unit including a quartz crystal resonator having a quartz crystal blank, a frame surrounding an outer periphery of the quartz crystal blank, and coupling members connecting the frame to the quartz crystal blank. Moreover, a lid member and a base member are attached to the frame and seal the resonator. One or more outer electrodes is formed over end surfaces of the frame, the lid member, and the base member on a side where the coupling members are coupled. The one or more outer electrodes has a machinery quality factor smaller than that of the frame.

An electronic component housing package and the like capable of reducing time of infrared heating operation are provided. An electronic component housing package includes an insulating substrate including a plurality of insulating layers stacked on top of each other, an upper surface of the insulating substrate being provided with an electronic component mounting section. The plurality of insulating layers each containing a first metal oxide as a major constituent. The insulating substrate further includes a first metal layer in frame-like form disposed on an upper surface of an uppermost one of the plurality of insulating layers. The first metal layer contains a second metal oxide which is higher in infrared absorptivity than the first metal oxide.

An electronic component housing package and the like capable of reducing time of infrared heating operation are provided. An electronic component housing package includes an insulating substrate including a plurality of insulating layers stacked on top of each other, an upper surface of the insulating substrate being provided with an electronic component mounting section. The plurality of insulating layers each containing a first metal oxide as a major constituent. The insulating substrate further includes a first metal layer in frame-like form disposed on an upper surface of an uppermost one of the plurality of insulating layers. The first metal layer contains a second metal oxide which is higher in infrared absorptivity than the first metal oxide.

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.