Patent classifications
H01L23/142
RF amplifier devices including interconnect structures and methods of manufacturing
A transistor amplifier includes a group III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die and an interconnect structure electrically bonded to the gate terminal, drain terminal and source terminal of the amplifier die on the first surface of the amplifier die and electrically bonded to an input path and output path of the transistor amplifier.
Laminate package of chip on carrier and in cavity
A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.
Wiring substrate, component embedded substrate, and package structure
A wiring substrate for improving connection reliability with an electronic component, a component embedded substrate that incorporates an embedded component into the wiring substrate, and a package structure including an electronic component mounted on the wiring substrate or the component embedded substrate. The wiring substrate includes a metal plate, and a wiring layer including a plurality of insulating layers and a conductive layer arranged on the plurality of insulating layers arranged on at least one principal surface of the metal plate. The plurality of insulating layers includes a first insulating layer to contact the principal surface of the metal plate and has a larger thermal expansion rate in the planar direction than the metal plate and a second insulating layer which is laminated on the first insulating layer to contact the first insulating layer and has smaller thermal expansion rate in the planar direction than the metal plate.
Element-accommodating package and mounting structure
An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting structure are provided. An element-accommodating package includes a metallic substrate, a frame, a first coaxial connector, a second coaxial connector, and a circuit board. A groove is provided between one side of the frame and a side surface of the circuit board and between a first signal line and a second signal line.
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.
Semiconductor package structure and method
In one embodiment, a semiconductor package structure includes a substrate having a well region extending from a major surface. An interposer structure is attached to the substrate within the well region. The interposer structure has a major surface that is substantially co-planar with the major surface of the substrate. An electrical device is directly attached to the substrate and the interposer structure. The interposer structure can be an active device, such as a gate driver integrated circuit, or passive device structure, such as an impedance matching network.
SEMICONDUCTOR DEVICE
A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump.
BIDIRECTIONAL SEMICONDUCTOR PACKAGE
Provided is a bidirectional semiconductor package in which the number of processes for manufacturing the bidirectional semiconductor package is reduced. According to present application, a portion between one end and the other end of the buffer wire is in contact with the lower surface of the upper DBC substrate and heat generated by the semiconductor chip is transferred to the upper DBC substrate.
ELECTROPHORETIC DEPOSITION FLUID, METAL CORE SUBSTRATE, AND METHOD FOR FABRICATING THE METAL CORE SUBSTRATE
The invention is directed to a metal core substrate having high thermal conductivity and high electrical insulating properties; an electrophoretic deposition fluid for use in fabrication of the metal core substrate; and a method for fabricating the metal core substrate. The electrophoretic deposition fluid is used during electrophoretic deposition, and contains ceramic particles for coating a metal substrate, and an organopolysiloxane composition which binds the ceramic particles.