In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

In an embodiment the dielectric layer comprises a fluoropolymer, a plurality of boron nitride particles, a plurality of titanium dioxide particles, a plurality of silica particles; and a reinforcing layer. The dielectric layer can comprise at least one of 20 to 45 volume percent of the fluoropolymer, 15 to 35 volume percent of the plurality of boron nitride particles, 1 to 32 volume percent of the plurality of titanium dioxide particles, 10 to 35 volume percent of the plurality of silica particles, and 5 to 15 volume percent of the reinforcing layer; wherein the volume percent values are based on a total volume of the dielectric layer.

A display panel and a display device are provided. In the display panel, a material of the first flexible layer and a material of the second flexible layer are different, and a direction of an internal stress of the first flexible layer and a direction of an internal stress of the second flexible layer are opposite. Therefore, the internal stress of the first flexible layer and the internal stress of the second flexible layer may eliminate each other. As a result, the first flexible layer and the second flexible layer will not be curled, and warpage will not occur on the display panel.

A copper base substrate of the present invention, in which a copper substrate, an insulating layer, and a circuit layer, are laminated in an order in the copper substrate, a ratio of a thickness (unit: .Math.m) to an elastic modulus (unit: GPa) at 100° C. is 50 or more in the insulating layer, and the circuit layer has an elastic modulus at 100° C. of 100 GPa or less.

A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

A substrate-based package semiconductor device is provided. The present disclosure further relates to a carrier including a plurality of non-singulated substrate-based package semiconductor devices and to a method of manufacturing the same. In embodiments in accordance with the present disclosure, the lowest insulating layer(s) has/have cavities arranged near and associated with one or more package terminals, and an inner wall of the cavities is covered with a conductive body that connects to the respective associated package terminal. Furthermore, the non-singulated substrate-based package semiconductor devices are separated by a separating region of the substrate, and the cavities are at least partially formed in the separating region.

An electronic device includes a carrier, a plurality of electronic elements and a connecting terminal. The carrier has at least one bonding pad. The electronic elements are disposed on the carrier, and each of the electronic elements includes a substrate. A distance between two adjacent substrates of the electronic elements is not less than 300 μm. The connecting terminal is disposed between one of the substrate and the carrier. One of the electronic elements are electrically connected to the at least one bonding pad via the connecting terminal.

Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.