A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.

A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.

In a built-in coil substrate, coil conductor patterns are provided on insulating base materials. Coil interlayer connection conductors, which provide interlayer connection between the coil conductor patterns, are provided on the insulating base materials and made of conductive paste. First and second external electrodes are provided on a first principal surface of a multilayer body. One of the coil conductor patterns is connected to the first external electrode by first-external-electrode connection conductors made of the conductive paste. Another one of the coil conductor patterns is connected to the second external electrode by a second-external-electrode connection conductor. The second-external-electrode connection conductor is a metal film provided in a through hole that extends through the multilayer body in a stacking direction in which the insulating base materials are stacked.

A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.

A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Methods of forming microelectronic package structures are described. Those methods/structures may include forming a high density region on a board comprising a first plurality of conductive structures disposed on a dielectric material on the board, wherein the first plurality of conductive structures comprises a first pitch between individual ones of the first plurality of conductive structures. A low density region on the board comprises a second plurality of conductive structures disposed on the dielectric material, wherein the second plurality of conductive structures comprises a second pitch between individual ones of the second plurality of conductive structures, wherein the second pitch is more than about twice the magnitude of the first pitch.

The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.

A component carrier for carrying electronic components, wherein the component carrier comprises an at least partially electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end, wherein the at least one electronic component is electrically contacted directly to the component contacting end, wherein at least an exterior surface portion of the coupling structure has homogeneous ablation properties and is patterned so as to have surface recesses filled with an electrically conductive wiring structure, and wherein the wiring contacting end is electrically contacted directly to the wiring structure.

The invention provides an electronic device that includes a first functional body, a second functional body, and at least one connection member connecting the first functional body to the second functional body. The at least one connection member has a spiral pattern, and is suspended in air to allow tor stretching, flexing or compressing.