H01L23/20

Low stress integrated device packages
10800651 · 2020-10-13 · ·

An integrated device package is disclosed. The integrated device package can include a packaging structure defining a cavity. An integrated device die can be disposed at least partially within the cavity. A gel can be disposed within the cavity surrounding the integrated device. A portion of the gel can be disposed between a lower surface of the integrated device die and an upper surface of the packaging structure within the cavity.

Low stress integrated device packages
10800651 · 2020-10-13 · ·

An integrated device package is disclosed. The integrated device package can include a packaging structure defining a cavity. An integrated device die can be disposed at least partially within the cavity. A gel can be disposed within the cavity surrounding the integrated device. A portion of the gel can be disposed between a lower surface of the integrated device die and an upper surface of the packaging structure within the cavity.

Process monitoring of deep structures with X-ray scatterometry

Methods and systems for estimating values of process parameters, structural parameters, or both, based on x-ray scatterometry measurements of high aspect ratio semiconductor structures are presented herein. X-ray scatterometry measurements are performed at one or more steps of a fabrication process flow. The measurements are performed quickly and with sufficient accuracy to enable yield improvement of an on-going semiconductor fabrication process flow. Process corrections are determined based on the measured values of parameters of interest and the corrections are communicated to the process tool to change one or more process control parameters of the process tool. In some examples, measurements are performed while the wafer is being processed to control the on-going fabrication process step. In some examples, X-ray scatterometry measurements are performed after a particular process step and process control parameters are updated for processing of future devices.

Oscillator, electronic apparatus, and vehicle

An oscillator includes a resonation element, a temperature sensitive element, a first package that houses the resonation element and the temperature sensitive element and is airtightly sealed, and a second package that houses the first package and is airtightly sealed. The first package includes a first base having a first recessed portion that is provided on one main surface side and a first lid that is joined to the first base so as to close an opening of the first recessed portion. The second package includes a second base having a second recessed portion that is provided on one main surface side and a second lid that is joined to the second base so as to close an opening of the second recessed portion.

Oscillator, electronic apparatus, and vehicle

An oscillator includes a resonation element, a temperature sensitive element, a first package that houses the resonation element and the temperature sensitive element and is airtightly sealed, and a second package that houses the first package and is airtightly sealed. The first package includes a first base having a first recessed portion that is provided on one main surface side and a first lid that is joined to the first base so as to close an opening of the first recessed portion. The second package includes a second base having a second recessed portion that is provided on one main surface side and a second lid that is joined to the second base so as to close an opening of the second recessed portion.

SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
20200219851 · 2020-07-09 ·

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

Hermetically sealed housing with a semiconductor component and method for manufacturing thereof

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

Hermetically sealed housing with a semiconductor component and method for manufacturing thereof

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

BYPASS THYRISTOR DEVICE WITH GAS EXPANSION CAVITY WITHIN A CONTACT PLATE

A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.

BYPASS THYRISTOR DEVICE WITH GAS EXPANSION CAVITY WITHIN A CONTACT PLATE

A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.