A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

An antenna device is provided. The antenna device includes a first substrate and a second substrate facing the first substrate. The first substrate includes an inner surface and an outer surface opposite the inner surface of the first substrate. The second substrate includes an inner surface and an outer surface opposite the inner surface of the second substrate. The antenna device also includes a die disposed between the first substrate and the second substrate, a redistribution layer disposed between the die and the inner surface of the second substrate, and an antenna unit electrically connected to the die via the redistribution layer. The antenna unit is arranged on at least one of the inner surface of the first substrate, the outer surface of the first substrate, the inner surface of the second substrate and the outer surface of the second substrate.

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.

Substrates that are bonding targets are bonded in ambient atmosphere via bonding films, including oxides, formed on bonding faces of the substrates. The bonding films, which are metal or semiconductor thin films formed by vacuum film deposition and at least the surfaces of which are oxidized, are formed into the respective smooth faces of two substrates having the smooth faces that serve as the bonding faces. The bonding films are exposed to a space that contains moisture, and the two substrates are overlapped in the ambient atmosphere such that the surfaces of the bonding films are made to be hydrophilic and the surfaces of the bonding films contact one another. Through this, a chemical bond is generated at the bonded interface, and thereby the two substrates are bonded together in the ambient atmosphere. The bonding strength can be improved by heating the bonded substrates at a temperature.

Substrates that are bonding targets are bonded in ambient atmosphere via bonding films, including oxides, formed on bonding faces of the substrates. The bonding films, which are metal or semiconductor thin films formed by vacuum film deposition and at least the surfaces of which are oxidized, are formed into the respective smooth faces of two substrates having the smooth faces that serve as the bonding faces. The bonding films are exposed to a space that contains moisture, and the two substrates are overlapped in the ambient atmosphere such that the surfaces of the bonding films are made to be hydrophilic and the surfaces of the bonding films contact one another. Through this, a chemical bond is generated at the bonded interface, and thereby the two substrates are bonded together in the ambient atmosphere. The bonding strength can be improved by heating the bonded substrates at a temperature.

Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

A method of manufacturing a semiconductor package includes: providing a substrate; providing a first die group comprising a first set of one or more dies, wherein the first die group is characterized by a first thickness; bonding a lower surface of the first die group to the substrate; providing a second die group comprising a second set of one or more dies, wherein the second die group is characterized by a second thickness larger than the first thickness; bonding the second die group to the substrate; providing a carrier substrate encapsulating at least one air gap, wherein the carrier substrate is characterized by a third thickness equal to or greater than a difference between the second thickness and the first thickness; and bonding a lower surface of the carrier substrate to an upper surface of the first die group.

A method of manufacturing a semiconductor package includes: providing a substrate; providing a first die group comprising a first set of one or more dies, wherein the first die group is characterized by a first thickness; bonding a lower surface of the first die group to the substrate; providing a second die group comprising a second set of one or more dies, wherein the second die group is characterized by a second thickness larger than the first thickness; bonding the second die group to the substrate; providing a carrier substrate encapsulating at least one air gap, wherein the carrier substrate is characterized by a third thickness equal to or greater than a difference between the second thickness and the first thickness; and bonding a lower surface of the carrier substrate to an upper surface of the first die group.