A power module is provided. The power module includes a substrate, and the substrate is used to carry components and pins of the power module. A circuit layer is disposed on the substrate, to complete an electrical connection between the carried components. The components and the pins are disposed on a same surface of the substrate, and the components and the pins are electrically connected by using the substrate. The power module further includes a sealing layer. The sealing layer is sleeved on the pins, the pins are partially exposed on a surface that is of the sealing layer and that faces away from a plastic packaging layer, and a space for accommodating the plastic packaging layer is formed between the sealing layer and the substrate.

A semiconductor module includes a laminate substrate having a first circuit board on which a semiconductor device having a plurality of upper surface electrodes including at least a main electrode is disposed and a second circuit board, a main terminal electrically connected to the main electrode, first and second auxiliary terminals electrically connected to first and second surface electrodes, and a main current wiring member electrically connecting the main electrode to the main terminal. A first path through which a first control current flows via the first auxiliary wiring is provided between the first upper surface electrode and the second auxiliary terminal, and a second path through which a second control current flows, via the main current wiring member, the second circuit board, and the second auxiliary wiring in this order, is provided between the second upper surface electrode and the second auxiliary terminal.

A semiconductor module includes a laminate substrate including a first circuit board on which a semiconductor device having a plurality of upper surface electrodes including a main electrode is disposed and a second circuit board, a main terminal electrically connected to the main electrode, an auxiliary terminal electrically connected to the one of the upper surface electrodes, and a main current wiring member electrically connecting the main electrode to the main terminal. A first path through which a first control current flows and a second path through which a second control current flows are provided between the one of the plurality of upper surface electrodes and the auxiliary terminal. The first control current flows via a first auxiliary wiring, and the second control current flows via the main current wiring member, the second circuit board and a second auxiliary wiring in this order.

A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.

Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling a ring to a substrate, and coupling an integrated circuit die to the substrate within the ring. A molding material is disposed around the integrated circuit die within the ring.

Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling a ring to a substrate, and coupling an integrated circuit die to the substrate within the ring. A molding material is disposed around the integrated circuit die within the ring.

A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip and so forth is formed; a rectangular parallelepiped case made of resin that is attached to the base plate and houses the substrate within; and a plurality of external terminals lower ends of which are fixed to the substrate with upper ends thereof being exposed on a top face of the case. The case is provided with a first case opening portion and a second case opening portion that are respectively formed by cutting off a front face and a rear face of the case from an upper edge thereof along a longitudinal direction thereof; and the top face of the case between the first case opening portion and the second case opening portion includes an external terminal holding portion to hold the plurality of external terminals along the longitudinal direction with the upper ends thereof being exposed. A sealing material is injected from the first case opening portion and the second case opening portion onto a top face of the substrate, and thereby the semiconductor module is sealed.