An electronic component cap for producing a package having a sealed region by being bonded to a base, having a brazing material-fused surface to which a brazing material is fused and a sealing surface corresponding to the sealed region. The brazing material-fused surface has a non-flat work surface formed by plastic working, and a ratio (Sc/Sf) of a surface area (Sc) of the brazing material-fused surface per unit area to a surface area (Sf) of the sealing surface per unit area satisfies 1<Sc/Sf1.6. The cross-sectional shape of the work surface may be one of various shapes such as a groove shape, an approximately V shape, and a circular-arc shape. The cap has a good wettability when a brazing material is fused. Also, the brazing material does not wet-spread excessively when the brazing material is melted again for sealing work.

The present disclosure provides a laminated structure suitable for semiconductor elements.

The laminated structure includes a first oxide layer having a trench structure on its surface and a second oxide layer laminated along the trench structure. A difference in thickness between centers of a bottom and a sidewall of the second oxide layer is less than 30%.

Disclosed herein is the formation of p-type transparent conducting oxides (TCO) having a structure of Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO. These structures disrupt the two-dimensional confinement of individual holes (the dominant charge carrier transport mechanism in pure NiO) creating three-dimensional hole transport by providing pathways for hole transfer in directions that are unfavorable in pure NiO. Forming these structures preserves NiO's transparency to visible light since the band gaps do not deviate significantly from that of pure NiO. Furthermore, forming Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO does not lead to hole trapping on O ions adjacent to Zn and Mg ions. The formation of these alloys will lead to creation of three-dimensional hole transport and improve NiO's conductivity for use as p-type TCO, without adversely affecting the favorable properties of pure NiO.

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.010.sup.11 cm.sup.2 eV.sup.1.

Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.010.sup.11 cm.sup.2eV.sup.1.

Systems and methods of etching a semiconductor substrate may include concurrent exposure of the semiconductor substrate to a chlorine-containing precursor and ultraviolet (UV) light. The semiconductor substrate may include exposed amorphous silicon. The semiconductor substrate may further include exposed crystalline silicon or underlying crystalline silicon. The methods may further include removing amorphous silicon faster than crystalline silicon.

A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a Si.sub.xH.sub.(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.

Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.010.sup.11 cm.sup.2 eV.sup.1.

A semiconductor package includes a molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. The molding member includes an extendible material which includes a first part having a warped shape, a second part extending from one end of the first part to be flat, and a third part extending from the other end of the first part to be flat, where first surfaces of the connectors are exposed at a surface of the molding member and second surfaces of the connectors are coupled to the chip.