The semiconductor device includes: a heat spreader; a semiconductor element joined to the heat spreader via a first joining member; a first lead frame joined to the heat spreader via a second joining member; a second lead frame joined to the semiconductor element via a third joining member; and a mold resin. In a cross-sectional shape obtained by cutting at a plane perpendicular to a one-side surface of the heat spreader, an angle on the third joining member side out of two angles formed by a one-side surface of the semiconductor element and a straight line connecting an end point of a joining surface between the third joining member and the semiconductor element and an end point of a joining surface between the third joining member and the second lead frame, is not smaller than 90° and not larger than 135°.

Semiconductor devices are arranged in a chain extending in a longitudinal direction have mutually facing end sides transverse the longitudinal direction and are coupled via tie bars located at the mutually facing end sides. The tie bars are provided with anchoring tips penetrating into an insulating package at mutually facing end sides of the devices. The tie bars can be deformed to extract the anchoring tips from the insulating package at the mutually facing end sides of the devices. Individual singulated devices are thus produced in response to the anchoring tips being extracted from the mutually facing end sides of the devices.

A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

A wheel sensor arrangement can include a first wheel speed sensor and a second wheel speed sensor. The first wheel speed sensor can include or be implemented with a first semiconductor die and can provide data regarding a speed of a rotating wheel. The second wheel speed sensor can also include or be implemented with a second semiconductor die and can provide data regarding the speed of the rotating wheel. The second semiconductor die can be galvanically isolated from the first semiconductor die. The wheel sensor arrangement can include a mold housing that forms around the first wheel speed sensor and the second wheel speed sensor. The mold housing can include a separation feature between the first sensor and the second sensor.

An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

A leadframe for semiconductor devices, the leadframe comprising a die pad portion having a first planar die-mounting surface and a second planar surface opposed the first surface, the first surface and the second surface having facing peripheral rims jointly defining a peripheral outline of the die pad wherein the die pad comprises at least one package molding compound receiving cavity opening at the periphery of said first planar surface.

A semiconductor structure includes a Through Silicon Via (TSV) and a protective ring disposed outside the TSV; the protective ring includes at least two protective layers arranged in parallel and surrounding the TSV; each of the protective layers includes a first protective structure and second protective structures disposed surrounding the first protective structure; the first protective structure is a polygonal structure; a number of sides of the polygonal structure is greater than or equal to 4; and the second protective structures are disposed on an inner side and an outer side of each corner area of the polygonal structure.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.