Provided are a heat dissipation structure, a method for forming a heat dissipation structure, and a semiconductor structure. The heat dissipation structure includes a first heat dissipation ring and a second heat dissipation ring. The first heat dissipation ring is formed in a dielectric layer around a Through Silicon Via (TSV) and in contact with the TSV. The TSV passes through a silicon substrate and the dielectric layer. The second heat dissipation ring is formed around the first heat dissipation ring, and in contact with the first heat dissipation ring. The second heat dissipation ring has a heat dissipation gap within it. A dimension of the second heat dissipation ring in a first direction is less than that of the first heat dissipation ring in the first direction. The first direction is a thickness direction of the silicon substrate.

Provided are a heat dissipation structure, a method for forming a heat dissipation structure, and a semiconductor structure. The heat dissipation structure includes a first heat dissipation ring and a second heat dissipation ring. The first heat dissipation ring is formed in a dielectric layer around a Through Silicon Via (TSV) and in contact with the TSV. The TSV passes through a silicon substrate and the dielectric layer. The second heat dissipation ring is formed around the first heat dissipation ring, and in contact with the first heat dissipation ring. The second heat dissipation ring has a heat dissipation gap within it. A dimension of the second heat dissipation ring in a first direction is less than that of the first heat dissipation ring in the first direction. The first direction is a thickness direction of the silicon substrate.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

A semiconductor package includes; laterally stacked semiconductor blocks disposed side by side in a first horizontal direction on a redistribution structure, wherein each semiconductor block among the laterally stacked semiconductor blocks includes laterally stacked semiconductor chips, a heat dissipation plate, and a first molding member on the laterally stacked semiconductor chips.

A semiconductor package includes; laterally stacked semiconductor blocks disposed side by side in a first horizontal direction on a redistribution structure, wherein each semiconductor block among the laterally stacked semiconductor blocks includes laterally stacked semiconductor chips, a heat dissipation plate, and a first molding member on the laterally stacked semiconductor chips.

Methods, systems, apparatus, and articles of manufacture to control load distribution of integrated circuit packages are disclosed. An example apparatus includes a heatsink, a base of the heatsink to be thermally coupled to a semiconductor device, and a rigid plate to be coupled to the semiconductor device and the base of the heatsink, the rigid plate stiffer than the base, the rigid plate distinct from a bolster plate to which the heatsink is to be coupled.

A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

Heat sink and heat sink arrangements are provided for an electronic device immersed in a liquid coolant. A heat sink may comprise: a base for mounting on top of a heat-transmitting surface of the electronic device and transferring heat from the heat-transmitting surface; and a retaining wall extending from the base and defining a volume. A heat sink may have a wall arrangement to define a volume, in which the electronic device is mounted. A heat sink may be for an electronic device to be mounted on a surface in a container, in an orientation that is substantially perpendicular to a floor of the container. Heat is transferred from the electronic device to liquid coolant held in the heat sink volume. A cooling module comprising a heat sink is also provided. A nozzle arrangement may direct liquid coolant to a base of the heat sink.