A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

graphite composite laminated heat-dissipating structure and a manufacturing method thereof are disclosed. The structure includes a metal substrate and a graphite heat-dissipating layer. The metal substrate has a first surface having a roughness ranging between 0.01 and 10 μm. The graphite heat-dissipating layer is composed of pure graphite and is directly formed on the first surface by means of physical vapor deposition using a carbon sputtering target. The graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 μm. The manufacturing method includes S1: directly forming a graphite heat-dissipating layer on a first surface of a metal substrate by means of physical vapor deposition using a carbon sputtering target after the metal substrate has received plasma treatment or infrared heating; and S2: stopping the physical vapor deposition when the graphite heat-dissipating layer has a thickness ranging between 0.05 and 2 μm.

An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

A thermally conductive and electrically insulating substrate is provided. The thermally conductive and electrically insulating substrate includes a thermally conductive base, an electrically insulating layer, and one or more metal sheets. The electrically insulating layer is disposed on the thermally conductive base, and the one or more metal sheets are disposed on the electrically insulating layer. The metal sheet is allowed to have one or more chips arranged thereon, and a surface of the metal sheet where the metal sheet is allowed to be engaged with the chip is not parallel to a surface of the electrically insulating layer where the electrically insulating layer is mated with the metal sheet.

Disclosed herein are power electronic modules formed by directly bonding a heat sink to a dielectric substrate using transition liquid phase bonding.

A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

A power module is provided with reduced power and gate loop inductance. The power module may be configured in a multi-layer manner with one or more organic substrates.

A heat-radiating sheet, in which when after sandwiching a heat-radiating grease between a heat-radiating sheet arranged on an aluminum plate and a glass plate, a heat cycle test is performed 100 cycles, an area ratio of an area of the heat-radiating grease after performing the heat cycle test of 100 cycles to an area of the heat-radiating grease before performing the heat cycle test is 1.0 to 2.0. A heat-radiating sheet laminate includes a heat-radiating sheet and a heat-radiating grease layer formed on the surface of the heat-radiating sheet. A structure includes the heat-radiating sheet, a heat-generating element, and the heat-radiating grease intervening between the heat-radiating sheet and the heat-generating element. A heat-radiating treatment method of a heat-generating element includes a step of applying a heat-radiating grease on the heat-radiating sheet and a step of arranging a heat-generating element on the heat-radiating sheet having the heat-radiating grease applied thereon.