A flip-chip semiconductor-on-insulator die includes a substrate layer, an active layer, an insulator layer between the substrate layer and the active layer, a first metal layer, and a first via layer between the active layer and the first metal layer. The die at least first and second contact pads and a transistor including a first terminal formed within the active layer. A first portion of the first terminal falls within a footprint of the first contact pad and a second portion of the first terminal falls within a footprint of the second contact pad.

Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. A trench that extends through the device layer and partially through the buried insulator layer is formed. An electrically-conducting connection is formed in the trench.

A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads, and an open cavity. A bridge die is in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, a power delivery bridge pad between the first plurality of bridge pads and the second plurality of bridge pads, and conductive traces. A first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads. A second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads. A power delivery conductive line is coupled to the power delivery bridge pad.

An electrostatic discharge protection circuit includes: a first electrostatic discharge protection device structure; a first contact pad above the first electrostatic discharge protection device structure in a cross-sectional view; and below the first electrostatic discharge protection device structure in the cross-sectional view, a metal connection coupling the first electrostatic discharge protection device structure to a second contact pad remote from the first contact pad, wherein the metal connection in the cross-sectional view only partially overlaps the first electrostatic discharge protection device structure.

According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

A semiconductor device including a biosensor with an on-chip reference electrode embedded within the semiconductor device, and associated manufacturing methods are provided. In some embodiments, a pair of source/drain regions is disposed within a device substrate and separated by a channel region. An isolation layer is disposed over the device substrate. A sensing well is disposed from an upper surface of the isolation layer overlying the channel region. A bio-sensing film is disposed along the upper surface of the isolation layer and extended along sidewall and lower surfaces of the sensing well. A reference electrode is disposed vertically between the bio-sensing film and the isolation layer.

A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.