An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.

The present invention relates to a method for manufacturing an insulating layer for a semiconductor package which can improve reliability and have excellent heat resistance by removing pores generated in the insulating layer during manufacture of an insulating layer for a semiconductor package using magnetic characteristics, and an insulating layer for a semiconductor package obtained using the method for manufacturing the insulating layer for a semiconductor package.

In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.

Provided is an etching method that can ameliorate defects caused by etching during processing contact holes in a semiconductor device. The etching method includes attracting and adhering a first polymerization film onto an insulating film disposed on a semiconductor layer that contains silicon by plasma of a first gas, removing the first polymerization film by plasma of a second gas, and simultaneously, oxidizing an upper surface of the insulating film to form an alteration layer, attracting and adhering a second polymerization film onto the alteration layer by plasma of a third gas, and removing the second polymerization film and the alteration layer by plasma of a fourth gas.

Provided is an etching method that can ameliorate defects caused by etching during processing contact holes in a semiconductor device. The etching method includes attracting and adhering a first polymerization film onto an insulating film disposed on a semiconductor layer that contains silicon by plasma of a first gas, removing the first polymerization film by plasma of a second gas, and simultaneously, oxidizing an upper surface of the insulating film to form an alteration layer, attracting and adhering a second polymerization film onto the alteration layer by plasma of a third gas, and removing the second polymerization film and the alteration layer by plasma of a fourth gas.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

A semiconductor structure includes a substrate, a TSV structure and a first protection structure. The substrate has a first region and a second region arranged adjacent to each other, and the first region comprises a functional device. The TSV structure is arranged in the second region and electrically connected to the functional device. The first protection structure is arranged around the TSV structure and electrically connected to the TSV structure. The first protection structure is located between the TSV structure and the functional device.