A dual damascene interconnect structure with a fully aligned via integration scheme is formed with a partially removed etch stop layer. Portions of the etch stop layer are removed prior to dual damascene patterning of an interlevel dielectric layer formed above metal lines and after such patterning. Segments of the etch stop layer remain only around the vias, allowing the overall capacitance of the structure to be reduced.

Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction in parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact and a gate jumper extending in the first direction. The gate jumper conductively connects to the gate finger at two or more locations that are spaced apart from each other along the first direction.

A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.

A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

A semiconductor monolithic IC includes a semiconductor substrate having a rectangular shape in plan view, multiple chiplets each comprising a circuit, wherein the multiple chiplets are disposed over the semiconductor substrate and are separated from each other by die-to-die spaces filled with a dielectric material, and a plurality of conductive connection patterns electrically connecting the multiple chiplets so that a combination of the circuit of the multiple chiplet function as one functional circuit. The chip region has a larger area than a maximum exposure area of a lithography apparatus used to fabricate the first and second circuits.

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

A semiconductor device includes a substrate, one or more transistors, a metal layer, one or more buried power rails, and at least one wall-via structure. The transistors and the metal layer are manufactured above a top surface of the substrate. The buried power rails are in one or more corresponding trenches in the substrate below the top surface of the substrate. At least one wall-via structure extends between the first buried power rail and the metal layer and electrically connects the first buried power rail to the metal layer. The wall-via structure includes a plurality of intermediate metal layers sandwiched between the first buried power rail and the metal layer. Alternatively, the wall-via structure includes a length that is greater than or equal to four times a basic length unit for components in layers between the first buried power rail and the metal layer for the semiconductor device.

A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.