A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming control circuitry of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth and fifth metal layers above second level; a global power distribution grid includes fifth metal, and local power distribution grid includes the second metal layer, where the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.