A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.

A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration.

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a bottom and sidewalls of the opening with a first substrate bias; forming a second barrier layer on the first barrier layer with a second substrate bias, the second substrate bias being greater than the first substrate bias, the first and second barrier layers forming collectively a barrier layer; removing a portion of the barrier layer on the bottom and on the sidewalls of the opening by bombarding the barrier layer with a plasma with a vertical substrate bias; and forming a second metal layer filling the opening.

A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.