A semiconductor device includes an insulating layer, a first conductive film, a second conductive film and a thin-film resistor. The insulating layer has a penetrating portion. The first conductive film is formed in the penetrating portion such that a recess is formed at an upper part of the penetration portion. The second conductive film is formed on an upper surface of the first conductive film and an inner surface of the penetrating portion. The thin-film resistor includes silicon and metal. The thin-film resistor is formed on the second conductive film and the insulating layer.

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

A nitride semiconductor device includes a conductive substrate, a nitride semiconductor layer on the substrate, first and second pads disposed above the semiconductor layer and connected to the semiconductor layer, first and second electrodes respectively connected to the first and second pads and extending on the semiconductor layer, a first control electrode extending between the first and second electrodes, and a guard ring disposed on the semiconductor layer, connected to the substrate, and surrounding a region in which the first and second pads, the first and second electrodes and the first control electrode are disposed such that a first capacitor is formed by the guard ring and the first pad and a second capacitor is formed by the guard ring and the second pad.

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

A semiconductor element includes: a first resistive layer; a second resistive layer provided separately from the first resistive layer and having a resistance value different from that of the first resistive layer; a first external connection electrode electrically connected to one end of the first resistive layer; a second external connection electrode provided separately from the first external connection electrode and electrically connected to one end of the second resistive layer; and a passivation film provided to cover the first and second external connection electrodes and having a first opening and a second opening to which top surfaces of the first and second external connection electrodes are partly exposed, wherein the first opening and the second opening having planar patterns with shapes different from each other.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.

A semiconductor device includes a semiconductor layer, a first region of a first conductivity type formed in the semiconductor layer and connected to a ground potential, a second region of a second conductivity type formed in the semiconductor layer, an insulating film formed on the semiconductor layer and covering the first region and the second region, an internal circuit, signal terminal for driving the internal circuit or to be driven by the internal circuit, a first wiring connecting the internal circuit and the signal terminal, a resistance element formed on the insulating film and interposed halfway through the first wiring, the resistance element including a first resistor facing the second region across the insulating film, and a second wiring connected to the first wiring on a side closer to the signal terminal than the resistance element and connecting the first wiring and the second region.