A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and/or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to a transceiver architecture for inter-die communication on-package using mm-wave/THz interconnects. In particular, amplifier-less transceivers are used in combination with on-package low loss transmission lines to provide inter-die communication. In embodiments, signals on the interconnect may be transmitted between up conversion mixers and down conversion mixers without any additional amplification. Other embodiments may be described and/or claimed.

An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.

A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.