The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the integrated circuit device. The integrated circuit device(s) also include external connection ports to transmit data to or receive data from outside the integrated circuit device, such as between integrated circuit devices. The integrated circuit device also includes remapping circuitry that remaps from a first connection between a first internal connection port of the internal connection ports and a first external connection port of the external connection ports to a second connection between a second internal connection port of the internal connection ports and a second external connection port of the external connection ports.

A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.

An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps.

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

An integrated circuit device that may include programmable logic fabric disposed on an integrated circuit die and a base die that may include clocking circuitry. Synchronization between logic resources in the programmable logic fabric may be performed using clock signals received from the clocking circuitry. The clocking circuitry in the base die may include phase-locked loops, delay-locked loops, clock trees, and other similar circuitry.

A semiconductor module according to embodiments includes a first external terminal, a second external terminal, a first semiconductor switch which is electrically connected between the first external terminal and the second external terminal and includes a first gate electrode, a second semiconductor switch which is electrically connected in parallel with the first semiconductor switch, between the first external terminal and the second external terminal, and includes a second gate electrode, a first fuse electrically connected between the first external terminal and the first semiconductor switch, and a second fuse electrically connected between the second external terminal and the first semiconductor switch.