A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

An antenna module includes an antenna substrate, a first semiconductor package, disposed on the antenna substrate, including a first connection member including one or more first redistribution layers, electrically connected to the antenna substrate, and a first semiconductor chip disposed on the first connection member, and a second semiconductor package, disposed on the antenna substrate to be spaced apart from the first semiconductor package, including a second connection member including one or more second redistribution layers, electrically connected to the antenna substrate, and a second semiconductor chip disposed on the second connection member. The first semiconductor chip and the second semiconductor chip are different types of semiconductor chips.

A semiconductor device package includes a first circuit layer and an emitting device. The first circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device is disposed on the second surface of the first circuit layer. The emitting device has a first surface facing the second surface of the first circuit layer, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The emitting device has a conductive pattern disposed on the second surface of the emitting device. The lateral surface of the emitting device and the lateral surface of the first circuit layer are discontinuous.

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

A component carrier including (a) a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; (b) an optical component embedded within the stack, wherein the optical component comprises an optically active portion; (c) an opening formed within the stack, wherein the optical component and the opening are spatially arranged and configured such that an optical communication between the optically active portion and an exterior of the stack is enabled; and (d) a protection structure extending at least partially around the optically active portion and/or the opening. The protection structure protects the optically active portion from a resin flow during an embedding of the optical component in the stack. A method for manufacturing such a component carrier.

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

A printed circuit board may include a substrate body portion, conductive patterns on a top surface of the substrate body portion, and a photosensitive insulating layer on the top surface of the substrate body portion and including an opening exposing at least one of the conductive patterns. The photosensitive insulating layer includes first to third sub-layers stacked sequentially. The first sub-layer includes an amine compound or an amide compound A refractive index of the second sub-layer is lower than a refractive index of the third sub-layer. A photosensitizer content of the second sub-layer is higher than a photosensitizer content of the third sub-layer.

An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.