A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

A semiconductor device A1 disclosed includes: a semiconductor element 10 having an element obverse face and element reverse face that face oppositely in a thickness direction z, with an obverse-face electrode 11 (first electrode 111) and a reverse-face electrode 12 respectively formed on the element obverse face and the element reverse face; a conductive member 22A opposing the element reverse face and conductively bonded to the reverse-face electrode 12; a conductive member 22B spaced apart from the conductive member 22A and electrically connected to the obverse-face electrode 11; and a lead member 51 having a lead obverse face 51a facing in the same direction as the element obverse face and connecting the obverse-face electrode 11 and the conductive member 22B. The lead member 51, bonded to the obverse-face electrode 11 via a lead bonding layer 321, includes a protrusion 521 protruding in the thickness direction z from the lead obverse face 51a. The protrusion 521 overlaps with the obverse-face electrode 11 as viewed in the thickness direction z. This configuration suppresses deformation of the connecting member to be pressed during sintering treatment.

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

An embedded power module includes a substrate, first and second semiconducting dies, first and second gates, and first and second vias. The first semiconducting die is embedded in the substrate and spaced between opposite first and second surfaces of the substrate. The second semiconducting die is embedded in the substrate, is spaced between the first and second surfaces, and is spaced from the first semiconducting die. The first gate is located on the first surface. The second gate is located on the second surface. The first via is electrically engaged to the first gate and the second semiconducting die, and the second via is electrically engaged to the second gate and the first semiconducting die.

A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.