Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.

A chip crack detection apparatus includes a function circuit and a die crack detection module surrounding the function circuit. The die crack detection module includes a front-end-of-line device layer, a laminated structure on the front-end-of-line device layer that includes a conducting wire in the laminated structure, a detection interface, and a capacitor at the front-end-of-line device layer. A first end of the conducting wire is configured to connect to a positive electrode of a power supply. A second end of the conducting wire is configured to connect to a negative electrode of the power supply. The capacitor is connected in parallel between the first end and the second end of the conducting wire. The detection interface is coupled with the conducting wire between the first end and the second end of the conducting wire. The detection interface is configured to detect whether a die crack occurs in the chip.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

A semiconductor module includes: a first metal plate including a first mount part joined with a bottom-surface electrode of a first switching element, a second mount part joined with a positive-electrode terminal, and a first narrow part between the first and second mount parts and being narrower than a part jointing the first switching element to the first mount part and the positive-electrode terminal; a second metal plate being joined with a bottom-surface electrode of a second switching element, and connected to a top-surface electrode of the first switching element; a third metal plate including a sixth mount part joined with a negative-electrode terminal, a seventh mount part connected to a top-surface electrode of the second switching element, and being narrower than the negative-electrode terminal, and a second narrow part between the sixth and seventh mount parts; and a snubber circuit connecting the first and second narrow parts.

An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.

A memory package structure includes a substrate, a memory chip and a plurality of resistors. The substrate has a plurality of pins. The pins include a plurality of data pins used to transfer data signal. The memory chip is located on the substrate. A plurality of bonding pads is located on the memory chip. The bonding pads include a plurality of data pads used to receive the data signal from data pins or transfer the data signal from the memory chip. The resistors is located on the substrate. Each data pad is connected to a corresponding one of the data pins through a corresponding one of the resistors.

Disclosed is a package and methods for making same. A package includes: a substrate having a first region comprising N number of metallization layers and a second region comprising M number of metallization layers, where M is less than N; a passive component located within the second region on a first surface of the substrate; and a die located within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the M number of metallization layers within the second region.

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.