The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

A method of producing an optoelectronic component includes providing an opto-electronic semiconductor chip including a layer sequence arranged on a substrate, wherein the layer sequence includes a contact side including two electrical contact locations, the contact side facing away from the substrate; arranging the optoelectronic semiconductor chip on an auxiliary carrier such that the contact side faces away from the auxiliary carrier; arranging a molding material above the auxiliary carrier such that a housing is formed that at least partly encloses the optoelectronic semiconductor chip, wherein the contact side is covered by the molding material; and detaching the housing from the auxiliary carrier.

Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes.

The present disclosure discloses a moistureproofing chip on film (COF) package for protecting the conductive pattern of the COF package against moisture. The moistureproofing COF package includes a base film having a conductive pattern formed on one surface thereof and having a solder resist formed on the conductive pattern and a moistureproofing tape attached to the top of the solder resist and configured to block moisture from being delivered to the conductive pattern through the solder resist.

The present disclosure discloses a moistureproofing chip on film (COF) package for protecting the conductive pattern of the COF package against moisture. The moistureproofing COF package includes a base film having a conductive pattern formed on one surface thereof and having a solder resist formed on the conductive pattern, and a moistureproofing coating layer formed on the solder resist by coating and configured to block moisture from being delivered to the conductive pattern through the solder resist.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.

A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.

A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.