In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

A method of processing a semiconductor wafer, in which a mask is formed: by cutting, with CO.sub.2 laser, a portion corresponding to a street, out of a temporary-adhesive of a surface protective tape to protect on a patterned face; carrying out dicing with SF.sub.6 plasma; and carrying out ashing, by removing a layer of the temporary-adhesive, with O.sub.2 plasma; a semiconductor chip; and a surface protective tape.

PROBLEM: To provide a multi-layer preform sheet capable of forming a highly reliable and high-quality electric interconnect, an electro-conductive bonding portion and so forth that are less likely to produce the Kirkendall void.

SOLUTION: A multi-layer preform sheet having at least a first layer and a second layer, the first layer being composed of a solder material that contains an intermetallic compound, and the second layer containing a first metal having a melting point of 300° C. or above, and a second metal capable of forming an intermetallic compound with the first metal.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

An example device in accordance with an aspect of the present disclosure includes a first layer and a second layer to be bonded to the first layer. The first and second layers are materials that generate gas byproducts when bonded, and the first and/or second layers is/are compatible with photonic device operation based on a separation distance. At least one bonding interface layer is to establish the separation distance for photonic device operation, and is to prevent gas trapping and to facilitate bonding between the first layer and the second layer.

An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles.

Embodiments may relate to a method of forming a microelectronic package with an integrated heat spreader (IHS). The method may include placing a solder thermal interface material (STIM) layer on a face of a die that is coupled with a package substrate; coupling the IHS with the STIM layer and the package substrate such that the STIM is between the IHS and the die; performing formic acid fluxing of the IHS, STIM layer, and die; and dispensing, subsequent to the formic acid fluxing, sealant on the package substrate around a periphery of the IHS.

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.