A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

A semiconductor device includes: a semiconductor element; a sealing resin; a gate terminal; a drain terminal; a source terminal; a heat dissipation plate electrically connected to the drain, and protruding from a second side intersecting with a first side of the sealing resin in top view; and a heat dissipation plate electrically connected to the drain, and protruding from a third side opposing the second side of the sealing resin in top view. At least a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate or a height position of a lower surface of a distal end portion of the heat dissipation plate and a height position of an upper surface of a proximal end portion of the heat dissipation plate are the same.

A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.

The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

A power module has a plurality of packaged power semiconductors, a printed circuit board, a heat sink, and possibly a sealing compound. The power semiconductors have electrically conductive connection elements and heat removal areas on respective outer sides. The power semiconductors are arranged on a cooling surface of the heat sink and has its heat removal area connected to the cooling surface of the heat sink to conduct heat, and the printed circuit board is arranged on a side of the power semiconductors that is opposite the heat sink in an orthogonal direction, wherein the connection elements of the power semiconductors make electrical contact with pads on the printed circuit board regions, for example, laterally beside an edge of the heat sink, in which a projection of the heat sink onto the printed circuit board in the orthogonal direction does not cover the connection elements.

A power module having a packaging structure includes a substrate having a first conductive area, a second conductive area, a third conductive area, a first fixing area and a second fixing area. The first, the second and the third conductive areas are electrically connected to a first terminal, a second terminal and a third terminal, and the first and the second fixing areas are electrically connected to a first switch set and a second switch set, so that they are in a parallel arrangement. The first terminal is a current input end, the second terminal is an intermediate end, and the third terminal is a current output end. When a current flows from the current input end to the intermediate end, or from the intermediate end to the current output end, the current flows straightly in order to reduce a crossover area and lower the stray inductance.

The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.

A semiconductor device has a single unit capable of improving adhesion to a cooling body and a heat dissipation performance, and an aggregate of the single units is capable of configuring any circuit at a low cost. A single unit includes copper blocks, an insulating substrate with a conductive pattern, an IGBT chip, a diode chip, a collector terminal pin, implant pins fixed to the chips by solder, a printed circuit board having the implant pins fixed thereto, an emitter terminal pin, a control terminal pin, a collector terminal pin, and a resin case having the above-mentioned components sealed therein. The copper blocks make it possible to improve adhesion to a cooling body and the heat dissipation performance. A plurality of single units can be combined with an inter-unit wiring board to form any circuit.

A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

A current shaping phase leg bus bar for power electronics systems includes a first terminal connector, a second terminal connector, insulated from the first terminal connector, and a third terminal connector, insulated from the first and second terminal connectors. At least one of the terminal connectors is a current shaping terminal connector that includes one or more layers having a plurality of pre-defined locations for electrical connections, said plurality of pre-defined locations including one or more first locations and a plurality of second locations, and includes one or more gaps within or among its one or more layers, to provide substantially balanced conductive pathways among its one or more first locations and its plurality of second locations.