A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

Composite materials including a thin-film layer of lateral p-n junctions can be employed in circuits or various components of electrical devices. A composite material comprises a thin-film layer including p-type regions alternating with n-type regions along a face of the thin-film layer, the p-type regions comprising electrically conductive particles dispersed in a first organic carrier and the n-type regions comprising electrically conductive particles dispersed in a second organic carrier, wherein p-n junctions are established at interfaces between the p-type and n-type regions.

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

A power semiconductor module includes a plurality of power semiconductor chips. A housing accommodates the power semiconductor chips. A first module electrode on a first side of the housing electrically is connected to a first chip electrode of the power semiconductor chips. A second module electrode on a second side of the housing electrically is connected to a second chip electrode. A surge arrester arrangement with a surge arrester is accommodated in the housing such that a first electrode of the surge arrester arrangement is provided at the first side of the housing and a second electrode of the surge arrester arrangement is provided at the second side of the housing. The power semiconductor chips are arranged in an annular region in the housing and the surge arrester arrangement is arranged within the annular region.

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Integrated circuits (ICs 110) are attached to a wafer (120W). A stabilization layer (404) is formed over the wafer to strengthen the structure for further processing. Unlike a conventional mold compound, the stabilization layer is separated from at least some wafer areas around the ICs by one or more gap regions (450) to reduce the thermo-mechanical stress on the wafer and hence the wafer warpage. Alternatively or in addition, the stabilization layer can be a porous material having a low horizontal elastic modulus to reduce the wafer warpage, but having a high flexural modulus to reduce warpage and otherwise strengthen the structure for further processing. Other features and advantages are also provided.

A power electronics module is provided having one or more power converter semiconductor components. The power electronics module further has a substrate having a first surface to which the one or more components are mounted, and having an opposing second surface from which project a plurality of heat transfer formations for enhancing heat transfer from the substrate. The power electronics module further has a coolant housing which sealingly connects to the substrate to form a void over the heat transfer formations of the second surface. The coolant housing has an inlet for directing a flow of an electrically insulating coolant into the void and an outlet for removing the coolant flow from the void, whereby heat generated during operation of the one or more components is transferred into the coolant flow via the substrate.

A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler.

An electronic component module includes an electronic component, a resin structure, a wiring portion, and a shield portion. The resin structure covers a second main surface and at least a portion of a side surface of the electronic component. The wiring portion is electrically connected to the electronic component. The shield portion includes a first conductor layer and a second conductor layer. The first conductor layer is spaced away from the electronic component between the electronic component and the resin structure, and has electrical conductivity. The second conductor layer is spaced away from the wiring portion between the wiring portion and the resin structure, and has electrical conductivity. In the shield portion, the first conductor layer and the second conductor layer are integrated.