Patent classifications
H01L25/11
POWER MODULE
A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
MODULE BOARD AND MEMORY MODULE INCLUDING THE SAME
A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
Encapsulation Structure and Encapsulation Method of Power Module
An encapsulation structure of a power module is disclosed in this application, which includes a power module and a liquid cooler. The power module includes a power module body, a metal baseplate, and heat dissipation finned tubes. A front side of the metal baseplate is connected to the power module body, and a back side of the metal baseplate is connected to the heat dissipation finned tubes. The metal baseplate has a protrusion part protruding. There are a plurality of grooves on a fluid pipe of the liquid cooler, a cavity exists between two adjacent grooves of the plurality of grooves, and the cavity is configured to communicate the two adjacent grooves. The power module body is lapped on the groove, a back side of the protrusion part is in contact with an edge surface of the groove, and the heat dissipation finned tubes are placed in the groove.
Power modules for ultra-fast wide-bandgap power switching devices
Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.
Semiconductor device and imaging apparatus
In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.
Semiconductor device and imaging apparatus
In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.
Circuit carrier arrangement and method for producing such a circuit carrier arrangement
A circuit carrier arrangement includes: a cooling plate (1) which has spacer and fastening elements (3) for connection to a printed circuit board (2) in a spaced-apart manner; a printed circuit board (2) which has bores (4) for receiving spring element sleeves (9); at least one power semiconductor component (10) which is connected by a soldered connection to the printed circuit board (2) and fastening elements (3) in the state in which it is fitted with the cooling plate (1) by means of plug-in connections (11) of spring-action configuration; and at least one spring element (5) having at least two spring element sleeves (9) between which a web (6) that is connected to the spring element sleeves (9) extends, and supporting elements (7) arranged on either side of said web and at least one spring plate (8) being arranged on said web.
Method for controlling controllable power semiconductor switches of a converter assembly with a plurality of switching modules having controllable power semiconductor switches, and a converter assembly with a control system configured for performing the method
A control system controls a plurality of controllable units with a central control device and further has a plurality of control modules, each of which is assigned to one of the units to be controlled. The central control device is set up to exchange digital data with each control module. The control modules form a connection network, wherein each control module is connected to at least one other control module via a communication line so that data exchange between them is possible. One of the control modules is directly connected to the central control device as the master node of the connection network, and the control modules are set up to form a communication network within the connection network, so that the data exchange between the central control device and each control module can be respectively carried out via an assigned communication path within the communication network.
Electronic Power Module
Electronic power modules are disclosed. In one example, an electronic power module includes a first aluminum substrate, a second aluminum substrate, and a third aluminum substrate arranged in a common plane. The electronic power module includes first gap separating the first aluminum substrate from the second aluminum substrate. The electronic power module includes a second gap separating the second aluminum substrate from the third aluminum substrate. The electronic power module includes a first semiconductor switching component electrically coupled to the first aluminum substrate and the second aluminum substrate. The electronic power module includes a second semiconductor switching component electrically coupled to the second aluminum substrate and the third aluminum substrate.
Package structure with warpage-control element
A package structure is provided. The package structure includes a semiconductor die and a molding compound layer surrounding the semiconductor die. The package structure also includes a conductive bump over the molding compound layer and a first polymer-containing layer surrounding and in contact with the conductive bump. The package structure further includes a second polymer-containing layer disposed over the first polymer-containing layer. A bottom surface of the conductive bump is below a bottom surface of the second polymer-containing layer.