A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1.sup.st cell and a 2.sup.nd cell placed next to each other in a cell width direction, wherein the 1.sup.st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1.sup.st cell, and connects a vertical field-effect transistor (VFET) of the 1.sup.st cell to a power rail of the 1.sup.st cell, wherein a 2.sup.nd cell includes a connector connected to a power rail of the 2.sup.nd cell, wherein the fin of the 1.sup.st cell and the connector of the 2.sup.nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1.sup.st cell and the connector of the 2.sup.nd cell are merged.

A method of forming a semiconductor structure is provided. The method includes forming a gate structure over an active region of a substrate, forming an epitaxial layer comprising first dopants of a first conductivity type over portions of the active region on opposite sides of the gate structure, the epitaxial layer, applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer, forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer, forming a contact region second dopants of a second conductivity type opposite the first conductivity type in the portion of the epitaxial layer not covered by the patterned photoresist layer, and forming a contact overlying the contact region.

An integrated circuit includes a first circuit cell having a first width and a second circuit cell having a second width that is wider than the first width by at least one contacted poly pitch. An equivalent circuit of the first circuit cell is the same as an equivalent circuit of the second circuit cell.

An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.

A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. Height of the second via is greater than height of the first via. The local interconnect line and the bit line are formed in the same metal layer. The bit line is thicker than the local interconnect line.

A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.