An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.

The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure, wherein the opening overlies at least a portion of the semiconductor device.

A semiconductor device is provided that is useful for ESD protection purposes. The device includes a semiconductor die; diode unit cells integrated on the die and being electrically connected between the first and second terminal, each unit cell includes a first region of a first charge type in the die and a second region of a second charge type in the die; an isolation structure arranged in the die, the isolation structure being configured to electrically isolate the unit cells from one another in the semiconductor die; and contacts including first contacts that are electrically connected to the first terminal and second contacts that are electrically connected to the second terminal, and each contact among the first and second contacts is electrically connected to the first region of a respective unit cell among the unit cells and to the second region of another unit cell among the unit cells.

Disclosed is an electrostatic protection circuit, an array substrate and a display device. The electrostatic protection circuit includes a first electrostatic discharge end, a second electrostatic discharge end and a signal line connecting end; a first discharge sub-circuit coupled between the first electrostatic discharge end and the signal line connecting end; and a second discharge sub-circuit coupled between the second electrostatic discharge end and the signal line connecting end. Each of the first discharge sub-circuit and the second discharge sub-circuit comprises at least one MOSFET, and gates of all MOSFETs comprised in the first discharge sub-circuit and the second discharge sub-circuit are not coupled with any one of the first electrostatic discharge end, the second electrostatic discharge end and the signal line connecting end.

Aspects of the present disclosure include one or more semiconductor electrostatic discharge protection devices. At least one embodiment includes a semiconductor electrostatic discharge device with one or more fingers divided into two segments with alternating p-diffusion and n-diffusion regions, with each region being associated with at least one of a portion of a diode and/or silicon-controlled rectifier (SCR).

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

The present disclosure provides an electrostatic protection circuit for display panels, a method, a display panel, and a display device. The display panel includes an array substrate, a chip on film (COF) substrate connected to the array substrate, and at least a remaining testing line. The electrostatic protection circuit includes at least a first electrostatic protection line configured to connect at least the remaining testing line to a grounding line of the COF substrate.

A transient voltage suppressing device includes a plurality of fingers arranged laterally along a major surface of an epitaxial layer. The plurality of fingers includes fingers of a first type and fingers of a second type. The first type and second type of fingers each include a silicon controlled rectifier (SCR) region and a junction diode region. The plurality of fingers of the second type are conductively coupled together by a second metal layer disposed over top a first metal layer and electrically insulated from the first metal layer. The first metal layer conductively couples the SCR region and junction diode region of the first type of finger.