Techniques are provided for protecting integrated circuits from plasma-induced electrostatic discharge (ESD) using a carrier substrate with integrated junctions. According to some embodiments, the various metal features within an interconnect region above a plurality of semiconductor devices are electrically coupled to one or more conductive pads on a bonded carrier substrate. The conductive pads provide a contact to underlying doped regions within the carrier substrate that form one or more PN junctions. This provides the ability to electrically ground metal features in the interconnect region via the carrier substrate. Formation of additional interconnect layers such as those provided during far back end of line (FBEOL) processing, can proceed while causing less plasma-induced ESD damage to the integrated circuit, because the interconnect region is connected to ground of carrier substrate by way of PN junctions, thus providing a discharge path for charge that develops during subsequent processing.

A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

An electronic device including a driving circuit substrate, a plurality of light emitting units, and a first passivation layer is provided. The driving circuit substrate includes a plurality of active elements. The light emitting units are disposed on the driving circuit substrate and electrically connected to the driving circuit substrate, and each of the plurality of light emitting units is five surfaces light emitting type. The first passivation layer covers the light emitting units and the driving circuit substrate for protecting the light emitting units. One of the active elements provides a current to a corresponding one of the light emitting units, such that lighting efficiency of the corresponding one of the light emitting units is ranged from 70% to 100%. The current includes a plurality of pulse currents spaced apart from each other, and time widths of the pulse currents are the same.

The present invention discloses a System on Chip, which includes a power supply pin, a ground pin, an anti-static unit and an anti-reverse connection unit, wherein the anti-static unit is connected between the power supply pin and the ground pin through the anti-reverse connection unit, the power supply pin and the ground pin of the System on Chip are connected to an external power supply; wherein, when the System on Chip is in normal operation, the anti-static unit performs ESD protection of the power supply pin through the conducted anti-static unit; whereas when the external power supply is reversely connected between the power supply pin and the ground pin of the System on Chip, the anti-reverse connection unit is cut off to prevent the reversely connected external power supply from directly connecting anode with cathode of the external power supply through the anti-static unit.

A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

A thin-film ESD protection device includes a semiconductor substrate including a low-resistivity portion at least adjacent to a first principal surface thereof; an insulating layer formed on the first principal surface; first and second input/output electrodes, and a ground electrode formed on a surface of the insulating layer. Moreover, a diode element and a capacitor element are formed adjacent to the first principal surface. The diode element is connected at a first end thereof to the first input/output electrode and connected at a second end thereof to the ground electrode. The capacitor element is connected at a third end thereof to the second input/output electrode and connected at a fourth end thereof to the ground electrode. The second end of the diode element and the fourth end of the capacitor element are connected by the low-resistivity portion of the semiconductor substrate to the ground electrode.

A system having a device for conducting an electrostatic discharge (ESD) current from a designated pin node. The system includes first and second pin nodes, and a switching device having a first switching threshold. The switching device includes a first, terminal coupled to a reference node, and a second terminal, coupled to the first pin node to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the reference node exceeding the first switching threshold. The switching device further includes a third terminal, coupled to the second pin node, to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the second pin node exceeding a second switching threshold.