A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1×10.sup.16 cm.sup.−3 to 2.4×10.sup.17 cm.sup.−3, a Zener diode region of a second conductivity type formed selectively in the semiconductor layer and forming a pn junction with the semiconductor layer, a Schottky metal disposed on the semiconductor layer, forming a Schottky junction with the semiconductor layer, and having a work function of 3 eV to 6 eV, and a JBS (junction barrier Schottky) structure including a plurality of second conductivity type regions formed selectively in the Schottky junction region of the semiconductor layer.

A semiconductor device includes a substrate and a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together. The semiconductor device further includes a gate stack over the substrate. The semiconductor device further includes a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions.

A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

A transformer structure includes at least three sections, each corresponding to metal layers of an integrated circuit. A first section of the at least three sections is electrically coupled to a third section with a second section disposed between the first and third sections. The at least three sections includes inductor coils, all of which are wound in a same direction and voltage phase starting at an outer terminal and continuing to an inner terminal of each inductor coil. At least one radial wiring channel passes through a portion of a coil in one of the three sections to provide an external connection to an internal terminal of the coil in at least one of the three sections.

The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.

An apparatus including a board, an inductor that is provided on the board, a guard ring that includes a first guard ring part provided to be adjacent to a circumference of the inductor and a second guard ring part provided to be adjacent to an outer side of the first guard ring part, in which one end of the second guard ring part is connected to one end of the first guard ring part, and a first power supply that is connected to another end of the first guard ring part and another end of the second guard ring part.

Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.