A solid-state quantum memory includes a vibrator supported in a displaceable (vibratable) manner on a substrate and a vibration exciter configured to excite the vibrator to vibrate. A rare-earth element is introduced into the vibrator and the introduced rare-earth element forms an electronic two-level system in the vibrator. The vibrator is supported on the substrate by a support. The substrate including a piezoelectric element formed from a piezoelectric material, as well as a first electrode and a second electrode formed by sandwiching the piezoelectric element, serves as the vibration exciter.

Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

Circuitries for controlling a power consuming device are disclosed. Methods for operating the circuitries and manufacturing the circuitries are also disclosed. In some embodiments, the circuit comprises a first thin-film transistor (TFT), a second TFT, and a storage capacitor. The first TFT is configured to output a current to a power consuming device. The second TFT is configured to provide a control voltage to the first TFT for controlling an amount of the current. The storage capacitor is configured to store the control voltage.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

A semiconductor device includes a layer of a semiconductor material in which is formed an active zone; a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in part the active zone; a plurality of second gates forming a plurality of columns; at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, and a first electrode and a second electrode situated on either side of the plurality of measurement gates in the active zone.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.