Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.

Some embodiments include a ferroelectric device having a ferroelectric insulative material which includes zinc. Some embodiments include a capacitor having a ferroelectric insulative material between a first electrode and a second electrode. The ferroelectric insulative material includes one or more metal-oxide-containing layers and one or more zinc-containing layers. Some embodiments include a memory array having a first set of first conductive structures and a second set of second conductive structures. The first conductive structures are coupled with driver circuitry, and the second conductive structures are coupled with sensing circuitry. The memory array includes an array of access devices. Each of the access devices is uniquely addressed by one of the first conductive structures in combination with one of the second conductive structures. Ferroelectric capacitors are coupled with the access devices. Each of the ferroelectric capacitors includes ferroelectric insulative material having zinc.

A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.

A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Provided is a method of preparing a dielectric film having a nanoscale three-dimensional shape and including an oxide, the oxide represented by R.sub.AM.sub.BO.sub.C where R is a divalent element and M is a pentavalent element, the method may include synthesizing a target material, the target material including the divalent element and the pentavalent element; and forming the oxide by depositing the divalent element and the pentavalent element, from the target material, onto a substrate such that the oxide includes a perovskite-type crystal structure, 1.3<B/A<1.7, and 9.0≤C<10.0.

The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.

Disclosed is a non-destructive large current-readout ferroelectric single-crystal thin film memory as well as a method of preparing the ferroelectric memory and a method of operating the ferroelectric memory. The large current-readout ferroelectric single-crystal thin film memory comprises a ferroelectric storage layer, which is a ferroelectric single-crystal storage layer. The non-destructive readout ferroelectric memory has a greatly increased read current in an on-state, and moreover, the data retention performance and data endurance performance are improved.

The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

A semiconductor memory device includes a substrate, and a capacitor structure on the substrate and including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer includes a lower interface layer on the lower electrode and doped with impurities of a first conductive type, an upper interface layer beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type, and a dielectric structure between the lower interface layer and the upper interface layer.