A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode, a dielectric layer disposed on the ferroelectric layer, charge trap sites disposed in an inner region of the dielectric layer, and a second electrode disposed on the dielectric layer. The dielectric layer may have a non-ferroelectric property. The dielectric layer and the ferroelectric layer are disposed between the first electrode and the second electrode and connected in series to each other. The semiconductor device may include charge trap sites distributed in an inner region of the dielectric layer having a non-ferroelectric property.

A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Disclosed are a high-dielectric and method of manufacturing the same, a target material used for manufacturing the high-dielectric, an electronic device including the high-dielectric, and an electronic apparatus including the electronic device. The high-dielectric includes a first material including oxygen and at least two components, and a second material different from the first materials. The first material is a dielectric having a dielectric constant greater than a dielectric constant of silicon oxide, and the second material is an element for reducing a crystallization temperature of the first material. The content of the second material with respect to the first material may be within a range that does not deteriorate leakage current characteristics of the first material. The content of the second material may be in a range of about 0.1 atomic % to about 10 atomic %, about 0.1 atomic % to about 8.5 atomic %, or about 0.1 atomic % to about 2 atomic %.

An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.

Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

An MIM capacitor includes a semiconductor substrate having a conductor layer thereon, a dielectric layer overlying the semiconductor substrate and the conductor layer, and a first capacitor electrode disposed on the dielectric layer. The first capacitor electrode partially overlaps with the conductor layer when viewed from above. A capacitor dielectric layer is disposed on the first capacitor electrode. A second capacitor electrode is disposed on the capacitor dielectric layer. At least one via is disposed in the dielectric layer and electrically connecting the first capacitor electrode with the conductor layer.

Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.