Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

A capacitor includes a first electrode including a first reinforcement material having a perovskite crystal structure; and a first metallic material having a perovskite crystal structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, wherein the first metallic material has greater a greater electronegativity than that of the first reinforcement material.

A thin film laminate structure, an integrated device including the same, and a method of manufacturing the thin film laminate structure are provided. The thin film laminate structure includes two or more dielectric layers, wherein at least one of the dielectric layers of the thin film laminate structure includes a compound represented by Formula 1 and having a perovskite-type crystal structure having a B/B′ composition ratio different from that of a remainder of the dielectric layers:

AB.sub.1-xB′.sub.xO.sub.3  <Formula 1> wherein, in Formula 1, A, B, B′, and x are the same as defined in the specification.

Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Some embodiments include a capacitor having a container-shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.

Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.