Patent classifications
H01L28/65
DUAL HYDROGEN BARRIER LAYER FOR MEMORY DEVICES
A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
STACKED FILM, ELECTRONIC DEVICE SUBSTRATE, ELECTRONIC DEVICE, AND METHOD OF FABRICATING STACKED FILM
A stacked film is a stacked film including an oxide film, and a metal film provided on the oxide film, in which the oxide film includes a ZrO.sub.2 film of which a main surface is a (001) plane, the metal film includes a Pt film or a Pd film that has a single orientation and of which a main surface is a (001) plane, and a [100] axis of the ZrO.sub.2 film and a [100] axis of the metal film are parallel to an interface between the oxide film and the metal film, and the axes of both are parallel to each other.
Capacitor and DRAM device including the same
A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.
Semiconductor device including an electrode lower layer and an electrode upper layer and method of manufacturing semiconductor device
A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.
Negative capacitance FinFET device and manufacturing method of the same
Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (L.sub.ext) from a side-wall of the gate stack to the drain electrode or the source electrode and the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.
FERROELECTRIC ELEMENT AND METHOD OF MANUFACTURING FERROELECTRIC ELEMENT
A method of manufacturing a ferroelectric element includes forming an insulating film on one side of a metal substrate by an electron beam (EB) vapor deposition method or a sputtering method; forming a metal film on the insulating film by the sputtering method; and forming a ferroelectric film on the metal film by a sol-gel method. The metal substrate includes iron (Fe) and nickel (Ni), and a content of the nickel (Ni) is greater than or equal to 30% and less than or equal to 40%.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.
METHOD FOR FABRICATING ELECTRONIC DEVICE
A method for fabricating an electronic device is provided, and the method comprises the steps of: forming a lower electrode on a substrate; forming a dielectric film on the lower electrode; forming an upper electrode on the dielectric film, the upper electrode including gold (Au); forming a refractory metal layer on at least one of upper or lower surface of the upper electrode, the refractory metal layer having a melting temperature higher than a melting temperature of the upper electrode; forming an insulating film to cover the lower electrode, the dielectric film, the upper electrode, and the refractory metal layer; and dry-etching the insulating film to form an opening therein, the upper electrode or the refractory metal layer being exposed at the opening.
CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A capacitor includes a first electrode including a first reinforcement material having a perovskite crystal structure; and a first metallic material having a perovskite crystal structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, wherein the first metallic material has greater a greater electronegativity than that of the first reinforcement material.
CRYSTALLINE BOTTOM ELECTRODE FOR PEROVSKITE CAPACITORS AND METHODS OF FABRICATION
A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.