A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [−1 0 0], [0 1 0], or [0 −1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.

The present disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the semiconductor device. According to an embodiment of the present disclosure, the semiconductor device may comprise: a substrate; a first device and a second device that are sequentially stacked on the substrate. Each of the first device and the second device comprises: a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked from bottom to top, and a gate stack around at least a part of an outer periphery of the channel layer, wherein sidewalls of the respective channel layers of the first device and the second device extend at least partially along different crystal planes or crystal plane families.

The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer. The semiconductor device includes a first semiconductor layer of a first conductivity type which is either a p-type or an n-type conductivity type, a source portion arranged so as to be in contact with the first semiconductor layer and configured as a semiconductor portion of a second conductivity type different from the first conductivity type, a source electrode arranged in ohmic contact with the source portion, a gate electrode arranged on at least one selected from surfaces of the first semiconductor layer via a gate insulating film interposed therebetween and capable of forming by an applied electric field, an inversion layer in a region of the first semiconductor layer near the surface of the first semiconductor layer contacting the gate insulating film, a second semiconductor layer of the first conductivity type arranged so as to be in contact with the inversion layer, and a drain electrode separated from the inversion layer and arranged in Schottky contact with the second semiconductor layer.

Embodiments relate to a semiconductor device including a trench with undercut structure including a substrate made of a first material; an insulation layer formed on an upper surface of the substrate; at least one trench penetrating the insulation layer toward the substrate; and at least one seed layer formed in the trench, the seed layer made of a second material which is different from the first material, and a method for manufacturing the same.

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nano sheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second source/drain epitaxial features, a first gate electrode layer disposed between the first and second source/drain epitaxial features, third and fourth source/drain epitaxial features, a second gate electrode layer disposed between the third and fourth source/drain epitaxial features, fifth and sixth source/drain epitaxial features disposed over the first and second source/drain epitaxial features, and a third gate electrode layer disposed between the fifth and sixth source/drain epitaxial features. The third gate electrode layer is electrically connected to the second source/drain epitaxial feature. The structure further includes a seventh source/drain epitaxial feature disposed over the third source/drain epitaxial feature and an eighth source/drain epitaxial feature disposed over the fourth source/drain epitaxial feature. The second gate electrode layer is disposed between the seventh and eighth source/drain epitaxial features.

A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.