The present invention provides a semiconductor device, comprising: a substrate (10); a stack of III-nitride transition layers (11) disposed on the substrate (10), the stack of III-nitride transition layers (11) maintaining an epitaxial relationship to the substrate (10); a first III-nitride layer (121) disposed on the stack of III-nitride transition layers (11); and a second III-nitride layer (122) disposed on the first III-nitride layer (121), the second III-nitride layer (122) having a band gap energy greater than that of the first III-nitride layer (121), wherein the stack of III-nitride transition layers (11) comprises a first transition layer (111), a second transition layer (112) on the first transition layer (111), and a third transition layer (113) on the second transition layer (112), and wherein the second transition layer (112) has a minimum aluminium molar ratio among the first transition layer (111), the second transition layer (112) and third transition layer (113). The present invention also relates to a method of forming such semiconductor device. The semiconductor device according to the present invention advantageously has a dislocation density less than or equal to 1×10.sup.9 cm.sup.−2 in the first III-nitride layer (121).

The present disclosure is directed to source/drain (S/D) epitaxial structures with enlarged top surfaces. In some embodiments, the S/D epitaxial structures include a first crystalline epitaxial layer comprising facets; a non-crystalline epitaxial layer on the first crystalline layer; and a second crystalline epitaxial layer on the non-crystalline epitaxial layer, where the second crystalline epitaxial layer is substantially facet-free.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

A method of manufacturing a silicon carbide epitaxial substrate includes: preparing a silicon carbide single-crystal substrate having a polytype of 4H and having a principal surface inclined at an angle θ from a {0001} plane in a <11-20> direction; growing a silicon carbide epitaxial layer on the principal surface having a basal plane dislocation, the basal plane dislocation having a portion extending in a <1-100> direction and a portion extending in a <11-20> direction; and irradiating the silicon carbide epitaxial layer with an ultraviolet light having a predetermined power and a predetermined wavelength for a predetermined period of time to stabilize the basal plane dislocation. After the irradiating, the basal plane dislocation does not move even when the basal plane dislocation is irradiated with an ultraviolet light having a power of 270 mW and a wavelength of 313 nm for 10 seconds.

The semiconductor device includes an Si chip which has a main surface facing a {100} plane, a trench which is formed by digging down the main surface and has an open end extending inclined in a <110> direction side with respect to a <100> direction in a plan view, and an oxide film which is constituted of an oxide of the Si chip and formed as a film on the main surface and at the open end.

A silicon carbide single crystal wafer and a preparation method therefor, a silicon carbide crystal and a preparation method therefor, and a semiconductor device. The surface of the silicon carbide single crystal wafer is such that an included angle between a normal direction and a c direction is 0-8 degrees, and aggregated dislocations on the silicon carbide single crystal wafer are less than 300/cm.sup.2; the aggregated dislocation is a dislocation aggregated condition in which the distance between the geometric centers of any two corrosion pits in the corrosion pits obtained after corrosion of melted KOH is less than 80 microns. Even if the dislocation density is relatively high, the aggregated dislocation density is relatively small, thereby increasing the yield of a silicon carbide-based devices.

A wiring substrate includes an insulating substrate including a first surface and a wiring conductor located at the insulating substrate, the insulating substrate containing multiple bulk crystallites of SiC with different polytypes. An electronic device includes the wiring substrate described above and an electronic component mounted on the wiring substrate. An electronic module includes the electronic device described above and a module substrate on which the electronic device is mounted.

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.