A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

A vertical field-effect transistor (FET), comprising a first doped region of a first material, said first doped region having a first doping and being formed on a surface of a substrate, a second doped region of said first material, said second doped region having a second doping and being formed on the first doped region, and a third doped region of said first material, said third doped region having a third doping and being formed on the second doped region, wherein the first doped region has a first width along a first direction parallel to said surface of the substrate, the second doped region has a second width along said first direction, the third doped region has a third width along said first direction, the second width being smaller than the first and third widths.

A manufacturing method for a semiconductor element includes a step of forming a mask partly having an opening and configured to cover a surface of a base substrate, and a step of forming a semiconductor layer containing a predetermined semiconductor material by inducing epitaxial growth along the mask from the surface of the base substrate exposed from an opening. A surface on the side closer to the semiconductor layer in the mask is formed of an amorphous first material that does not contain an element to serve as a donor or an acceptor in the predetermined semiconductor material.

According to one embodiment, a semiconductor device includes first, second, third nitride members, first, second, third electrodes, and a first insulating member. The first nitride member includes a first face along a first plane, a second face along the first plane, and a third face. The third face is connected with the first and second faces between the first and second faces. The third face crosses the first plane. The first face overlaps a part of the first nitride member. The second nitride member includes a first nitride region provided at the first face. The third nitride member includes a first nitride portion provided at the second face. The first electrode includes a first connecting portion. The second electrode includes a second connecting portion. The third electrode includes a first electrode portion. The first insulating member includes a first insulating region.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of α-Ga.sub.2O.sub.3 or an α-Ga.sub.2O.sub.3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 μm. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 μm or greater and 64 μm or less.

A reliability of a semiconductor device is ensured, and performance of the device is improved. A semiconductor device including a region 1A and a region 2A includes an n-type semiconductor substrate TS having a front surface BS1, BS2 and a back surface SUB, a IGBT formed on a semiconductor substrate in a region 1A, and a diode formed on the semiconductor substrate SUB in a region 2A. And a thickness T1 of the semiconductor substrate SUB in the region 1A is smaller than a thickness of the semiconductor substrate T2 in the region 2A.

The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

To further reduce contact resistance when a current or a voltage is taken out from a metal layer. A conductive structure including: an insulating layer; a metal layer provided on one surface of the insulating layer to protrude in a thickness direction of the insulating layer; and a two-dimensional material layer provided along outer shapes of the metal layer and the insulating layer from a side surface of the metal layer to the one surface of the insulating layer.