The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.

There is provided a semiconductor element containing gallium nitride. The semiconductor element includes a semiconductor layer including a first surface having a first region and a second region that is a projecting portion having a strip shape and projecting relative to the first region or a recessed portion having a strip shape and being recessed relative to the first region. Of the first surface, at least one of surfaces of the first region and the second region includes a crystal plane having a plane orientation different from a (000-1) plane orientation and a (1-100) plane orientation.

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.

A wide-gap semiconductor substrate enables formation of a device having low power loss while maintaining high mechanical strength. The wide-gap semiconductor substrate (70) is obtained by placing a wide-gap semiconductor substrate onto a platen (15) disposed in a processing chamber (11) and etching and thinning only a first substrate region (70a), where a device (50) is formed, of the wide-gap semiconductor substrate by means of plasma generated from an etching gas. In the wide-gap semiconductor substrate (70), a connecting portion as a peripheral edge of the first substrate region (70a) connecting to a second substrate region (70b) surrounding the first substrate region (70a) includes an arc portion having a predetermined radius of curvature.

Disclosed is a cellular structure of a silicon carbide MOSFET device, and a silicon carbide MOSFET device. The cellular structure comprises: second conductive well regions located on two sides of the cellular structure and arranged within the surface of a drift layer, first conductive source regions located within the surfaces of the well regions, and a gate structure located at the center of the cellular structure and in contact with the source regions, the well regions, and the drift layer. The cellular structure further comprises a source metal layer located above the source regions and forming ohmic contact with the source regions; on two sides of the cellular structure, side trenches are formed downwardly on regions of the drift layer that are not covered by the well regions; Schottky metal layers forming Schottky contact with the drift layer below the side trenches are arranged in the side trenches.